Recursive Intelligence Automates Chip Layouts to Slash Design Times

Sequoia Capital

AI-generated custom silicon architectures will unlock a Cambrian explosion of hardware efficiency, rendering traditional human-engineered grid layouts obsolete.

AI-assisted summary of AI That Designs Its Own Chips: Ricursive's Anna Goldie and Azalia Mirhoseini — original source. Check the original for full context.

Source published: 2026-05-06

Detailed notes

## Background Published by Sequoia Capital on YouTube on May 6, 2026, this video features Anna Goldie and Azalia Mirhoseini introducing their company, Ricursive Intelligence (referred to in notes as Recursive Intelligence). The page description outlines their thesis that AI should design the chips that train AI, detailing a three-phase plan to accelerate chip design, democratize custom silicon, and vertically integrate their own chips and models.

## TL;DR In this presentation, AlphaChip co-creators Anna Goldie and Azalia Mirhoseini outline their vision for Recursive Intelligence, a company aimed at closing a self-improving loop between AI software and hardware. They introduce a three-phase strategy to accelerate the bottlenecked chip design process with tools operating up to 100,000x faster, establish a "designless" platform for custom workloads, and eventually achieve full vertical integration. Additionally, they discuss the technical realities of this shift, explaining how their proprietary AI tools produce highly efficient, organic-looking chip layouts that radically depart from traditional human-engineered grid designs.

## Atmosphere & style The presentation carries an innovative, visionary, and forward-thinking tone, driven by the deep professional and academic chemistry of its co-founders. It feels like a high-level masterclass in deep tech engineering, blending a sense of disruptive ambition with rigorous technical credibility. The dynamic between the speakers is collaborative and grounded, evoking an atmosphere of profound transformation as they describe how rigid, human-designed structures are giving way to curved, organic, AI-generated shapes.

## Key takeaways - [00:03](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=3s) Neural networks are achieving superhuman performance in semiconductor design, rapidly replacing traditional tools across the industry. - [00:03](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=3s) Recursive Intelligence, founded by the co-creators of AlphaChip, operates on the core thesis that AI should design chips and chips should power AI to create a self-improving loop. - [00:03](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=3s) The founders share a 10-year professional history collaborating across Google Brain, Anthropic, DeepMind, and Stanford. - [01:31](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=91s) AlphaChip, a deep reinforcement learning agent developed by the founders, has been proven in production for Google's TPUs, Axion CPUs, Pixel phones, and external chips like MediaTek. - [01:31](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=91s) Phase 1 of Recursive Intelligence's vision focuses on eliminating the massive bottlenecks of physical design and design verification. - [01:31](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=91s) Delays in semiconductor production carry immense financial stakes, with a single day of delay for an Nvidia Blackwell chip costing an estimated $225 million. - [01:31](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=91s) Phase 2 aims to democratize chip design by allowing clients to input workloads and receive specialized, factory-ready GDS2 architectures without needing internal teams. - [01:31](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=91s) Phase 3 involves full vertical integration, where the company plans to build its own chips and train its own models for unmatched cost and capability. - [04:08](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=248s) Recursive Intelligence is redesigning traditional chip tools to run up to 100,000x faster, enabling AI reinforcement learning loops to thrive on near-instant feedback. - [04:08](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=248s) The company has developed a proprietary Static Timing Analysis (STA) engine that matches commercial tool fidelity while running 1,000x faster. - [04:08](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=248s) The company introduces the concept of a 'designless' era, functioning like TSMC's fabless model but allowing companies to offload hardware design entirely. - [07:04](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=424s) Customization is positioned as the primary catalyst for a 'Cambrian explosion of chips' optimized for specific workload needs like power, throughput, or scale. - [07:04](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=424s) The company's competitive advantage lies in a hybrid team of LLM experts behind systems like Claude, Gemini, and Grok alongside veteran hardware engineers. - [07:04](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=424s) AI-designed chip layouts feature curved, organic-looking shapes that minimize wire length and improve performance, contrasting with rigid human-designed grids. - [07:04](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=424s) Custom AI silicon economics are highly viable because scaling compute turns design into a configurable knob, and even a 1% efficiency gain yields massive financial returns.

## Detailed walkthrough ### [00:03](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=3s) Introduction to AlphaChip and Recursive Intelligence

Neural networks are rapidly replacing traditional tools across various industries, and one of the most exciting applications is in semiconductor design. In this domain, neural networks are achieving superhuman performance in specific parts of the chip design process. Anna and Azalia, the co-creators of AlphaChip at Google, are introduced to the stage. AlphaChip was used across multiple generations of Google's Tensor Processing Units (TPUs) and other hardware. The duo has now co-founded a new company, Recursive Intelligence, to take this technology to the next level.

Anna and Azalia share a deep professional history, having worked together closely for the last 10 years across Google Brain, Anthropic, and DeepMind. Their academic and professional pursuits ran in parallel; Anna pursued her PhD while working full-time, and Azalia joined the Stanford faculty. Their core thesis at Recursive Intelligence is that "chips are the fuel for AI," and conversely, AI should be used to design, optimize, and automate the chip design process. This creates a recursive, self-improving loop between AI software and its physical hardware substrate.

- **Founders:** Anna and Azalia, co-creators of AlphaChip. - **Company Name:** Recursive Intelligence. - **Core Thesis:** Using AI to design chips and chips to power AI, closing a recursive self-improving loop. - **Historical Collaboration:** 10 years of working together across Google Brain, Anthropic, DeepMind, Stanford, and PhD programs.

---

[01:31](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=91s) The Legacy of AlphaChip and the Three Phases of Recursive Intelligence

The journey began in 2018 with the development of AlphaChip, a deep reinforcement learning agent capable of generating superhuman chip layouts. Published in *Nature*, the work's true significance lay in its real-world application. AlphaChip was used in the actual tape-out of multiple generations of Google's AI accelerator chips (TPUs), Google's Axion data center CPUs, Pixel phones, autonomous vehicle chips, and chips for external companies like MediaTek. Recursive Intelligence was founded to expand this AI-driven automation across the entire chip design workflow.

Anna outlines the company's vision in three distinct phases: * **Phase 1: Accelerating the Chip Design Process.** Currently, the two longest bottlenecks in chip design are physical design (placing and routing billions of standard cells and transistors) and design verification (verifying logical correctness). Each phase can take up to a year and require hundreds or thousands of human experts. The stakes are incredibly high; for instance, a single day of delay for an Nvidia Blackwell chip can cost a company an estimated $225 million in lost opportunity cost. * **Phase 2: Democratizing Chip Design.** The company aims to build a platform where a customer can input a specific workload (such as a next-generation Claude model) and receive a custom-designed architecture optimized for that workload, all the way to a "GDS2 clean" format ready for manufacturing. This would allow any company with a large-scale workload to benefit from custom silicon without needing an in-house team of hundreds of chip experts. * **Phase 3: Vertical Integration.** In the final phase, Recursive Intelligence plans to build its own chips, train its own models, and co-evolve them to serve intelligence at an unmatched price and capability level.

---

[04:08](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=248s) Technical Approach and the "Designless" Era

Azalia explains the traditional chip design flow, which spans from initial architecture design to final sign-off before fabrication. Today, human experts navigate these phases using commercial tools that can take days to run a single optimization iteration. Recursive Intelligence's approach is to redesign these underlying tools to make them 100,000x faster. Because AI and reinforcement learning loops thrive on fast iteration, these ultra-fast tools allow AI agents to exponentially learn and co-optimize across massive design spaces.

As a concrete example of their progress, Azalia highlights their proprietary Static Timing Analysis (STA) engine, a notoriously challenging component of physical design. Their tool correlates with industry-standard commercial tools with high fidelity but runs 1,000x faster. This rapid feedback loop allows their outer-loop AI to run multiple iterations and optimize design recipes, yielding significantly higher performance than a single standard iteration.

This technological leap enables what they call the "designless" era. Just as the "fabless" model enabled by TSMC allowed companies like Apple and Nvidia to focus on design rather than manufacturing, Recursive Intelligence wants to be the platform that handles the hardware design itself. This allows software and AI companies to focus purely on applications and modeling while Recursive handles the underlying compute hardware.

- **Tool Speedup Target:** Redesigning traditional tools to make them up to 100,000x faster. - **Static Timing Analysis (STA) Engine:** Achieves a 1,000x speedup while maintaining high fidelity with commercial tools. - **The "Designless" Concept:** Allowing companies to offload physical chip design entirely, focusing only on their software workloads.

---

[07:04](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=424s) Customization, Team Expertise, and Q&A

While there are currently only a few mainstream chips for AI inference, the future demands a massive leap in performance. Azalia argues that customization is the key to unlocking this performance. By building chips tailored to specific workloads, Recursive Intelligence hopes to spark a "Cambrian explosion of chips" optimized for different trade-offs, such as low power, high throughput, or massive frontier model scale. The company's team is uniquely suited for this task, combining LLM experts who have worked on Claude, Gemini, and Grok with veteran chip design experts.

During the Q&A session, an audience member asks about the physical appearance of AI-designed chips. Anna explains that while human experts design highly regular, grid-aligned layouts, AlphaChip and their current models generate "curved, organic-looking shapes." These organic layouts minimize wire length and improve performance, though they initially shocked traditional physical design engineers.

Another question addresses the economics of specialized chips and whether producing thousands of custom chips can ever be as cost-effective as mass-producing a single architecture like Nvidia's Hopper. Azalia explains that by scaling compute, they can dramatically reduce design times and costs, effectively turning design into a configurable "knob." Furthermore, given the massive scale of modern AI workloads, even a 1% improvement in chip efficiency for a frontier model translates into massive financial and operational gains, making customization highly viable.

## Notable quotes > [00:03](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=3s) chips are the fuel for AI — Anna and Azalia

> [01:31](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=91s) Accelerating the Chip Design Process. — Anna

> [01:31](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=91s) Democratizing Chip Design. — Anna

> [01:31](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=91s) Vertical Integration. — Anna

> [04:08](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=248s) designless — Azalia

> [07:04](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=424s) Cambrian explosion of chips — Azalia

> [07:04](https://www.youtube.com/watch?v=K05Dh-QjM8c&t=424s) curved, organic-looking shapes — Anna

## Mentioned AI Ascent 2026, Anna Goldie, Azalia Mirhoseini, Ricursive Intelligence, Recursive Intelligence, Google Brain, DeepMind, Anthropic, Stanford, AlphaChip, Google, TPUs, Tensor Processing Units, Axion, Pixel, MediaTek, Nvidia Blackwell, Claude, GDS2, Static Timing Analysis (STA) engine, TSMC, Apple, Nvidia, Gemini, Grok, Nvidia's Hopper

[Source](https://www.youtube.com/watch?v=K05Dh-QjM8c)

中文简报

Recursive Intelligence 推进芯片布局自动化以大幅缩短设计周期 AI 生成的定制芯片架构将释放硬件效率的“寒武纪大爆发”，使传统的人工设计网格布局走向淘汰。在本次演讲中，AlphaChip 联合创作者 Anna Goldie 和 Azalia Mirhoseini 阐述了对 Recursive Intelligence 的愿景，该公司旨在构建 AI 软件与硬件之间的自我改进闭环。他们提出了一个分三阶段的战略，利用运行速度提升最高达 100,000 倍的工具加速遭遇瓶颈的芯片设计流程，构建面向定制工作负载的“无设计”（designless）平台，并最终实现完全的垂直整合。此外，他们还探讨了这一转变的技术现实，解释了其专有 AI 工具如何生成高效、呈有机形态的芯片布局，从而彻底颠覆传统的人工工程网格设计。 AlphaChip 联合创始人 Anna Goldie 与 Azalia Mirhoseini 创立 Recursive Intelligence，其核心理念是通过 AI 设计芯片、芯片赋能 AI，构建软硬件协同自我进化的递归闭环。 (0:03) 公司规划了三阶段路线：第一阶段解决物理设计与验证的核心瓶颈；第二阶段打造“无设计（designless）”平台，直接交付可投产的 GDS2 芯片；第三阶段实现自研芯片与大模型的全栈垂直整合。 (1:31) Recursive 致力于将底层芯片设计工具提速最高达 100,000 倍，其静态时序分析（STA）引擎已在保持高保真度的前提下实现 1,000 倍加速，大幅加快 AI 强化学习的迭代效率。 (4:08) 与人类工程师规整的网格布局不同，AI 设计的芯片呈现出能显著缩短走线长度的有机曲线形态；借助算力压缩设计成本，定制化专用芯片正在成为提升前沿 AI 负载能效的关键路径。 (7:04)

Reading summary

AlphaChip co-creators Anna Goldie and Azalia Mirhoseini have founded Recursive Intelligence to close a self-improving loop where AI designs semiconductor hardware and advanced chips power AI. The founders argue that radically accelerating underlying design tools can eliminate multi-year engineering bottlenecks and enable a new era of customized silicon. From AlphaChip to Full Vertical Integration (1:31) Building on AlphaChip—a reinforcement learning system published in Nature and deployed across Google's TPUs, Axion CPUs, and external hardware like MediaTek—Recursive Intelligence plans an automated chip design platform structured in three phases. The first phase targets the primary bottlenecks in modern chip creation: physical design (placing and routing billions of standard cells and transistors) and design verification. Goldie notes that each phase currently takes up to a year and requires hundreds of engineers, where delays carry severe costs—such as an estimated $225 million daily opportunity loss for an Nvidia Blackwell chip. The second phase aims to democratize hardware by turning workload specifications (such as a Claude model) directly into fabrication-ready "GDS2 clean" files, removing the need for customers to maintain in-house chip design teams. In the third phase, the founders envision full vertical integration, where the company designs proprietary chips, trains its own AI models, and co-evolves hardware and software together to optimize price and compute performance. Re-architecting EDA Tools for the 'Designless' Era (4:08) Traditional electronic design automation (EDA) software runs slowly, often requiring days for a single design iteration and severely limiting reinforcement learning agents that depend on rapid feedback. Recursive Intelligence is redesigning these core tools with a target speedup of up to 100,000x. As an initial milestone, Mirhoseini cites their proprietary Static Timing Analysis (STA) engine, which operates 1,000x faster than traditional commercial tools while maintaining high-fidelity correlation, allowing an outer-loop AI to rapidly test and optimize multiple design recipes. The founders frame this technical shift as the foundation for a "designless" industry model. Analogous to how TSMC's "fabless" revolution permitted companies like Apple and Nvidia to outsource fabrication and focus entirely on architecture, Recursive Intelligence aims to handle physical hardware design completely, letting software and model developers outsource chip design. Workload Customization and Organic Physical Layouts (7:04) Addressing current industry reliance on a handful of mainstream AI chips, Mirhoseini predicts a transition toward workload-specific silicon optimized along distinct trade-offs, such as extreme power efficiency or high throughput. While mass-producing standard architectures has historically offered superior economies of scale, Mirhoseini contends that scaling compute reduces automated design costs into a flexible parameter. Furthermore, at the extreme scale of frontier AI training, even a 1% gain in hardware efficiency provides substantial financial and operational returns. This AI-driven approach also alters the physical layout of microchips. According to Goldie, while human chip designers traditionally rely on rigid, grid-aligned placements, reinforcement learning systems generate curved, organic-looking geometries. Although non-intuitive to human engineers, these organic shapes measurably reduce overall wire lengths and enhance performance. Recursive Intelligence argues that automated custom silicon can outperform general-purpose accelerators across massive workloads, though validating this thesis will depend on whether automated, ultra-fast design tools can consistently match commercial sign-off reliability when deployed across external fabrication pipelines.

精炼阅读摘要

Recursive Intelligence联合创始人Anna Goldie与Azalia Mirhoseini提出，半导体芯片是人工智能发展的底层燃料，而人工智能算法应反向自动化并优化芯片设计，二者构成相互促进的递归自迭代闭环。该团队主张通过将底层工具链速度提升数个数量级，从解决物理设计与验证瓶颈切入，推动芯片行业迈入软件公司无需自建硬件团队的“无设计”（designless）时代。技术渊源与三阶段自迭代路线 (1:31) 两位创始人此前在Google共同研发了基于深度强化学习的芯片布局智能体AlphaChip，该成果发表于《Nature》，并已在多代Google TPU加速器、Axion数据中心CPU、Pixel手机芯片、自动驾驶芯片以及联发科（MediaTek）的外包芯片中实际投片验证。基于软件与硬件相互优化的核心论点，Recursive Intelligence规划了三阶段演进路径：第一阶段聚焦于加速芯片设计中最耗时的物理设计与设计验证环节，两位创始人指出这两个阶段目前各需耗费多达一年时间与数百上千名工程专家，例如Nvidia Blackwell芯片若延期一天可能造成约2.25亿美元的机会成本损失。在后续规划中，第二阶段旨在实现芯片设计的平民化，客户仅需输入类似新一代Claude模型的工作负载，系统便可自动生成针对该负载优化且达到可制造标准的GDS2版图，使缺乏庞大硬件团队的公司也能获取定制芯片；第三阶段则计划进行完全的垂直整合，由公司自主设计芯片并训练自研模型，通过软硬件协同演进提供低成本与高算力服务。底层工具重构与无设计范式 (4:08) 当前芯片设计流程从架构定义到流片签署，主要依赖单次迭代耗时数天的商业工具，限制了算法探索复杂设计空间的能力。Azalia Mirhoseini解释称，Recursive Intelligence的技术核心在于重构底层工具，目标是将运行速度提升最高达10万倍，从而为强化学习智能体提供超高频反馈循环，使其能够进行更广泛的参数搜索与多轮联合优化。作为具体进展，该团队推出了专有的静态时序分析（STA）引擎。据团队介绍，该工具在与业界标准商业工具保持高保真度关联的前提下，运行速度提升了1000倍，外层AI由此得以运行海量迭代方案以输出更优的综合设计指标。基于工具链效率的大幅提高，创始人提出了“无设计”（designless）商业模型：如同台积电开创的代工模式让Apple和Nvidia等Fabless企业无需自建晶圆厂，Recursive Intelligence希望接管底层芯片物理实现，使AI和软件企业能够彻底剥离硬件设计负担，专注于模型研发与上层应用。定制化经济学与有机物理形态 (7:04) 针对芯片定制化能否与大规模量产通用架构（如Nvidia Hopper）竞争的疑问，Azalia Mirhoseini主张，随着算力规模扩展，芯片设计耗时与成本可被转化为可灵活配置的参数。考虑到现代前沿AI模型的运行体量，专用芯片即使仅带来1%的效率提升，也能转化为可观的财务与运营收益，因此未来将出现涵盖低功耗、高吞吐等不同方向的“寒武纪式芯片大爆发”。目前该团队结合了参与过Claude、Gemini和Grok等大语言模型研发的人员与资深硬件设计专家。在物理实现层面，AI生成的芯片版图展现出了与传统工程截然不同的形态。Anna Goldie指出，人类工程师受设计工具与思维定势限制，通常构建高度规则化、网格对齐的几何布线；而AlphaChip及其当前算法则倾向于生成弯曲、类似生物形态的有机走线形状。这类非规则结构在初期令传统物理设计工程师感到意外，但在实际测试中证实能有效缩短导线总长度并提升芯片性能。 Recursive Intelligence展示了通过超高速EDA工具与强化学习颠覆芯片物理设计与定制流程的愿景。然而，将自动化方案从单项静态时序分析扩展至完整制造就绪的GDS2版图输出，以及在经济层面抗衡通用GPU的庞大生态壁垒，仍有待更广泛的跨工序工程落地与实际制造验证。

Source quotes

[0:03] Anna and Azalia: chips are the fuel for AI [1:31] Anna: Accelerating the Chip Design Process. [1:31] Anna: Democratizing Chip Design. [1:31] Anna: Vertical Integration. [4:08] Azalia: designless [7:04] Azalia: Cambrian explosion of chips [7:04] Anna: curved, organic-looking shapes

Original transcript

[0:03] One of the themes that we've heard [0:04] throughout the day is that neural nets [0:06] are replacing a lot of traditional [0:07] tools. And I think one of the most [0:10] exciting application categories where [0:11] we've actually seen that come to life is [0:14] within chip design, where neural nets [0:15] are now becoming superhuman at certain [0:18] parts of the semiconductor design [0:20] process. And so I'm thrilled to [0:22] introduce Anna and Azalia. They were the [0:24] co-creators of AlphaChip, which did [0:26] exactly this at Google and [0:28] was used on multiple generations of TPU [0:30] and have now started a company to to [0:32] build this. Thank you and welcome Anna [0:34] and Azalia. [0:36] Thank you so much. [0:37] >> [applause] [0:42] >> Hi everyone. Azalia and I are so excited [0:44] to be here today to talk about our new [0:46] company, Recursive Intelligence, where [0:49] we're doing AI for chip design and chip [0:51] design for AI. [0:53] We've been working together closely for [0:55] the last 10 years across Google Brain, [0:57] Anthropic, DeepMind, and then because it [1:00] wasn't enough to work at one [1:02] institution in parallel, I started my [1:04] PhD while continuing to work full-time [1:06] and Azalia joined the Stanford faculty. [1:08] So you know, we have been working in [1:11] many different [1:12] places together for a long time. But our [1:14] thesis in this company is that chips are [1:17] the fuel for AI and that we should be [1:20] using AI to design, to optimize, and [1:23] automate the chip design process and [1:25] close this recursive self-improving loop [1:27] between AI and its physical substrate. [1:31] We started this direction in 2018 with [1:35] our work on AlphaChip, [1:37] where we developed a deep reinforcement [1:38] learning agent that was capable of [1:40] generating superhuman chip layouts. [1:43] This work was published in Nature, but [1:44] the interesting part about it, in our [1:46] opinion, was that it was actually used [1:48] in the tape-out of real chips. So the [1:50] last four generations now of Google's AI [1:53] accelerator chips, TPU, [1:55] data center [clears throat] CPUs called [1:57] Axion, [1:58] Pixel phones, and also autonomous [2:01] vehicle chips, and in addition to [2:04] adoption by external companies like [2:05] MediaTek. [2:07] And so we decided to start this company [2:10] to take this work to the next level and [2:13] take on all of the chip design workflow. [2:17] We see the company in three phases. So [2:20] currently we're in phase one, where we [2:22] want to accelerate the chip design [2:24] process. So today there are two long [2:26] poles. One is physical design, [2:29] and which is placing the billions of [2:32] standard cells or billions of [2:34] transistors and routing billions of [2:36] these components onto a chip canvas, and [2:39] design verification, which is verifying [2:41] the correctness of the logic of that [2:42] chip. Each of these can take up to a [2:44] year and involves hundreds or thousands [2:46] of human experts. And the stakes are [2:48] extremely high. So we've heard estimates [2:51] like one day of delay of an Nvidia [2:54] chip cost like a Blackwell cost a [2:56] company something like $225 million in [2:58] lost opportunity cost. So we want to [3:01] help existing chip makers get to market [3:03] faster, build faster, cheaper, and more [3:05] environmentally friendly chips. [3:08] But I think in phase two of the company, [3:09] we want to democratize chip design. So [3:12] we want to become a platform for [3:13] designing new hardware, where we can [3:15] take as input like a workload, say like [3:18] the next quad model, design an [3:20] architecture that massively accelerates [3:23] that workload, and then do the entire [3:25] design process all the way to GDS2 [3:27] clean, which is the format that we send [3:29] to the fabs for manufacturing. [3:31] And in that case, we can massively [3:33] unlock the number of customers that we [3:36] could serve. Like any company that has a [3:38] workload that that they serve at [3:39] sufficient scale could benefit from [3:42] custom chips, even if they don't have [3:43] teams of hundreds or thousands of human [3:45] experts. [3:46] And then phase three of the company [3:48] would be vertical integration. So if we [3:50] have this capability to quickly design [3:52] highly performant chips, why not build [3:55] our own chips? Why not train our own [3:57] models and co-evolve them? [3:59] And serve intelligence at a price or [4:01] capability that would be impossible to [4:03] match. [4:04] So Azalia's going to talk a bit more [4:06] about our our approach in this company. [4:08] Yes. [4:09] If I can stop on this slide. So on the [4:12] right side, we're showing you the flow, [4:14] the traditional flow for chip design. It [4:16] starts with architecture design and it [4:19] goes all the way to sign-off, and that's [4:21] what you send to the fabs. And as you [4:23] can see, there are many components here, [4:25] and the way these [4:27] kind of phases are done today with human [4:29] experts in the loop, working with [4:32] commercial tools that sometimes takes [4:35] days to run for a single iteration of an [4:38] optimization. So our approach here at [4:40] Recursive is to first redesign the way [4:43] these tools [4:45] perform, make them 100,000x faster, and [4:49] then they're primed to be used with AI [4:51] because, as you know, our AIs really [4:55] like fast iteration loops and they can [4:57] just exponentially learn more and [4:59] co-optimize across a very, very large [5:02] space if we enable them to do so. [5:05] So by co-designing across the stack, we [5:08] what this enables is unlocking massive [5:11] performance improvements and time to [5:13] market, which comes from both the [5:15] co-design and the automation. [5:17] To just show you a glimpse into what we [5:20] are building, here is an STA, a static [5:22] timing analysis engine. This is one of [5:25] the [5:26] a very challenging component of physical [5:28] design. And what we are showing here is [5:30] that we are we have built a tool that [5:32] correlates with the commercial tools [5:35] very high fidelity, and what we can do [5:38] here is do so a thousand x faster. Now [5:41] imagine if you're doing an AI tool use [5:44] or an RL loop, we can we now have this [5:48] kind of feed feedback signal that we can [5:50] use in the optimization, we can do a lot [5:52] more with it. Here is a example of how [5:55] our outer outer loop, our AI works with [5:58] this tool. Like here, early on is what [6:01] we get with a single iteration of our [6:04] inner loop, but as the AI optimizes [6:06] around the recipes that are possible to [6:09] use these tools with, we can get [6:11] significantly more performance. [6:15] So taking a step back, what Recursive [6:20] is enabling is a new era, which we call [6:23] designless, just like fabless, um [6:27] enabled by companies like TSMC, [6:30] made made it such that we can have [6:32] Nvidia, Apple, other companies focus on [6:35] designing chips and send off the the [6:37] designs for fabrication elsewhere. We [6:40] want to be the platform for [6:43] chip design, so companies can focus on [6:46] the application, modeling, and other [6:48] layers, and we can be the compute and [6:51] hardware that enable those applications. [6:54] And the impact would be that we we can [6:56] democratize chip design and enable a lot [6:59] more variety and performance types of [7:02] chips possible. [7:04] So [7:06] right now, [7:07] there are a few mainstream chips for AI [7:10] inference. But as you can imagine, and [7:12] as a lot of talks and conversations [7:14] today allude to, we are going to need a [7:16] whole lot more performance in the coming [7:18] years. And one way to unlock a lot of [7:21] performance is through customization. So [7:24] when we build chips that are truly [7:25] customized to the workloads that we are [7:27] serving, and we at Recursive want to be [7:30] the platform that enables this Cambrian [7:33] explosion of chips, so we can build a [7:36] lot more variety of chips that are [7:38] really custom to the types of workloads [7:40] that [7:41] the companies and the users care about. [7:44] And if you can imagine, these chips can [7:46] enable a very large workload like a [7:49] frontier model, or it can they can [7:52] enable like a very low power or high [7:54] throughput or other kind of variations [7:57] of performance that we that we would [7:59] need. [8:01] And finally, we have an amazing team. [8:04] Our company is a little unusual in that [8:06] we have this [8:08] subset of people who are very expert in [8:10] LLM. They have [8:12] they have worked on um [8:14] Quad, Gemini, um [8:17] Grok, and such in the past. And now that [8:19] we have put them together with these [8:20] experts in chip design, and so it's a [8:24] very great mix and we are very glad that [8:27] we get to build together. [8:30] Yeah, and with that we can conclude the [8:32] talk. Happy to answer questions. [8:34] >> [applause] [8:38] >> Hey, [8:39] any word on the the shape of the chip [8:41] placements that you end up seeing out of [8:44] these models compared to the Oh shoot, [8:46] we should have shown some of the [8:47] layouts. So I think just like in [8:49] AlphaChip, we're seeing these kind of [8:51] curved, organic-looking [8:53] shapes to our placements. So human [8:55] experts, they tend to make these very [8:56] aligned, [8:58] regular-looking placements, but the the [9:00] AI-generated ones look more like [9:03] yeah, organic, curved, which minimizes [9:06] wire length, improves performance, but [9:08] it was kind of shocking to physical [9:10] design engineers when they first saw [9:11] them. A question on the [9:13] cost of these specialized chips. I [9:15] totally understand that you could make a [9:17] better chip with AI and have better [9:19] placements and stuff. But you I think [9:21] Azalia was also making the point that [9:22] you could make specialized chips. [9:25] How does the scale work out? I don't [9:26] know the first principles of chip [9:28] design. Can you make thousands of [9:29] different chips and make them as cheaply [9:31] as one Hopper architecture? [9:35] I mean there's yeah, go ahead. Yes, [9:37] there is [9:38] definitely what we are doing here is [9:40] like we are going into a new regime [9:43] where we have we can work compute into [9:46] our advantage. So by scaling compute, we [9:49] can reduce the run times to design the [9:51] chip and also to enable more performant [9:54] chips. So we are basically introducing a [9:56] knob. Um now, through customization, [10:00] given the scale at which AI workloads [10:02] are going to be run, the economy of [10:04] scales is going to is is working itself, [10:07] right? Even a 1% improvement in a chip [10:11] that serves a frontier model is a is a [10:14] massive uh gain and success if you can [10:16] if you could enable that. But, at [10:18] different scales, we have different [10:20] performance gains. And again, what we [10:21] are talking here is that we are using [10:23] compute to bring automation and better [10:26] performance. And and and that's a knob [10:29] that we can play with. [10:32] >> [applause and cheering]