@Scale
Google engineered its Virgo scale-out network fabric with multi-plane skinny links and fixed-overhead telemetry to connect up to one million AI chips across campus data centers without training job disruptions.
AI-assisted summary of Virgo: Scale-out Data Center Network for AI | Jeongkeun "JK" Lee, Google — original source. Check the original for full context.
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Detailed notes
## Background This talk by Jeongkeun "JK" Lee from Google was published on YouTube by @Scale on August 27, 2026. The description notes that it introduces Virgo, a dedicated scale-out accelerator-to-accelerator network fabric engineered for deterministic latency, maximum resilience, and massive horizontal scale to power next-gen TPUs and NVIDIA Vera Rubin platforms.
## TL;DR Google engineer JK Lee details Virgo, a dedicated scale-out data center network fabric designed to meet the extreme multi-building demands of modern AI workloads. He outlines four core design principles—integrated supercomputer design, built-in resiliency, high-resolution telemetry, and deployment speed—that shaped Virgo's 2-layer flat architecture and multi-plane "skinny link" topology. The talk highlights how Consolidated In-Band Congestion Signaling (CEC) and sub-millisecond telemetry expose invisible micro-bursts to maintain high goodput. Looking ahead, Lee invites industry collaboration through the Ultra Ethernet Consortium to standardize adaptive routing and scale RDMA across multi-metro long-haul campuses.
## Atmosphere & style The presentation carries an authentic, enthusiastic, and highly technical tone that balances deep architectural rigor with nostalgic industry reflections. Lee brings a grounded, engineer-to-engineer presence to the stage—symbolized by his classic 2018 conference t-shirt—making complex network concepts accessible through vivid side-by-side dashboard comparisons. Watching the talk feels like an insider look into hyper-scale infrastructure design, driven by a genuine passion for how once-niche telemetry innovations are now solving critical real-world AI bottlenecks.
## Key takeaways - [00:05](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=5s) Google's networking evolution spans four main inflection points: the Internet Era (Jupiter, Orion, Apollo), the Streaming Era (QUIC, TCP BBR), the Cloud Era (Andromeda, PSP, Falcon), and the modern AI Era. - [00:41](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=41s) AI network design requires treating the entire building or campus as an integrated supercomputer co-designed tightly with specific accelerator generations. - [00:41](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=41s) The core design mandate for modern AI networks is to build native resiliency so underlying infrastructure failures remain completely invisible to AI training workloads. - [06:13](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=373s) Google's AI data center network is split into three distinct layers forming a flat compute domain: the Scale-in domain (ICI for intra-pod), the Virgo Scale-out fabric (inter-pod), and the Jupiter front-end fabric (storage and WAN). - [08:36](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=516s) Virgo uses high-radix switches to create a flat, 2-layer non-blocking topology, reducing switch hops and packet latency. - [08:36](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=516s) Virgo implements multi-plane isolation using 'skinny links' at lane speeds down to 30 Gbps, ensuring an 8-plane architecture retains 87.5% bandwidth even if an entire plane fails. - [08:36](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=516s) The multi-plane skinny-link architecture enables non-blocking Virgo clusters to scale up to 1,000,000 TPU/GPU accelerator chips in a single logical domain across campus sites. - [13:05](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=785s) Consolidated In-Band Congestion Signaling (CEC) aggregates telemetry metrics across hops (using MIN/MAX functions) to maintain a constant header overhead while pinpointing exact bottlenecks. - [13:05](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=785s) CEC is being standardized through the Ultra Ethernet Consortium (UEC) and featured at SIGCOMM 2026 based on Google's production deployment experience. - [15:47](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=947s) Sub-millisecond telemetry monitoring is essential because traditional 30-second average metrics hide severe 100% link utilization micro-bursts caused by synchronized AI workloads. - [17:39](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=1059s) Future development focuses on expanding Virgo to multi-metro fabrics over hundreds or thousands of kilometers, adapting CEC for long-haul, high-RTT RDMA performance. - [17:39](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=1059s) Google is calling on the industry to establish multi-vendor standardization around adaptive routing, fast route-change notifications, and in-band telemetry protocols.
## Detailed walkthrough Here is a detailed, faithful walkthrough of the transcript, capturing the technical specifics, architectural principles, data points, and overall narrative texture.
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[00:05](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=5s) Introduction and Historical Context: A Decade of Networking Inflection Points
Jeongkeun "JK" Lee introduces himself, representing his engineering team at Google. Reflecting on his career trajectory, he recalls starting as a researcher at HP Labs before joining Barefoot Networks—widely known for the P4 programming language and Tofino switch ASICs. He proudly notes that he is wearing a t-shirt from the 2018 Networking @Scale conference, expressing deep gratitude for the open industry perspectives shared at these events over the years.
Moving to the present era of 2026, Lee maps out Google's networking journey through four fundamental inflection points leading up to today's massive AI demands:
1. **The Internet Era:** Built to power global services like Search, Maps, and Gmail. Google had to re-architect data center networks from the ground up, giving birth to the Jupiter fabric, paired with Orion for SDN control, and pioneering Apollo optical circuit switching (OCS) for flexible, intra-building expansion. 2. **The Streaming Era:** Driven by the need to deliver high-quality video with minimal jitter to millions of end devices. This motivated new transport and congestion protocols like QUIC and TCP BBR. 3. **The Cloud Era:** Demanded extreme multi-tenancy, high reliability, and strict security guarantees. Google engineered Andromeda, gRPC for microservices, and moved network functions directly into hardware—such as PSP for inline hardware encryption and Falcon for reliable transport. 4. **The AI Era:** Characterized by exponential growth in foundational model parameter sizes. This makes AI training exceptionally network-intensive, requiring exponentially higher network bandwidth alongside extremely strict delay bounds.
Because AI supercomputers now span across multiple data center buildings and whole campuses, traditional scale constraints cause "basically everything to break." The core mandate for modern network design is to make these inevitable underlying infrastructure failures completely invisible to AI workloads.
- **Speaker background:** JK Lee (Google; formerly HP Labs, Barefoot Networks). - **Conference artifact:** Wearing a classic 2018 @Scale event t-shirt. - **Key Google historical milestones:** Jupiter (fabric), Orion (SDN), Apollo (OCS), QUIC, TCP BBR, Andromeda, gRPC, PSP (encryption), Falcon (transport).
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[00:41](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=41s) Four Core Principles for AI Network Design
To tackle the extreme conditions of AI supercomputing, Lee presents four foundational principles that guided the engineering and execution of Virgo—Google's new scale-out data center network:
1. **Integrated Supercomputer Design:** The network must be engineered as part of the entire building or campus functioning as a single, unified supercomputer optimized specifically for one or two AI use cases, rather than acting as generic, multi-purpose infrastructure. Hardware components (switches, optics, fiber) are co-designed and specced in lockstep with each accelerator generation (GPUs/TPUs). Consequently, traditional requirements like backward/forward compatibility or flexible expansion (which Jupiter and Apollo solved) are no longer primary constraints. 2. **Bake-in Resiliency:** Training jobs must not crash or restart due to a single link or switch failure. Resilience must be built natively into the physical topology and control loops. 3. **High-Resolution, High-Quality Telemetry:** Hardware resiliency alone is insufficient. Transport protocols, congestion control, load balancing in the data plane, and management-plane debugging all rely heavily on timely, granular telemetry to extract maximum performance and availability from the physical network. 4. **Execution and Deployment Speed:** Networking must never be the bottleneck delaying the deployment of multi-billion-dollar AI supercomputers. This requires minimizing switching layers (which reduces latency while cutting raw material requirements) and designing fiber/rack layouts that align directly with real-world building construction phases. Modeling physical dimensions and physical space constraints in software beforehand prevents costly first-time deployment issues on-site.
- **Design Philosophy:** Dedicated AI fabric > general-purpose infrastructure. - **Cycle Alignment:** Network hardware lifecycle is tightly bound to accelerator (GPU/TPU) generations. - **Deployment Efficiency:** Fewer switching layers = lower latency + fewer materials to physically deploy.
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[06:13](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=373s) Virgo Architecture: The Three-Layer Flat Compute Domain
Google shifted away from traditional general-purpose network structures toward a flat, specialized, low-latency architecture. Under this model, the data center operates as three distinct, specialized network layers forming one unified compute domain:
``` +-----------------------------------------------------------------+ | JUPITER FABRIC | | (Front-End: Storage, General Compute, Global WAN & Multi-Site) | +-------------------------------+---------------------------------+ | +-------------------------+-------------------------+ | | +-----v---------------------------+ +---------v-----------------------+ | VIRGO SCALE-OUT FABRIC | | VIRGO SCALE-OUT FABRIC | | (Inter-Pod Accelerator Network)| | (Inter-Pod Accelerator Network) | +-----------------+---------------+ +-----------------+---------------+ | | +-----------------v---------------+ +-----------------v---------------+ | SCALE-IN DOMAIN (ICI) | | SCALE-IN DOMAIN (ICI) | | (Intra-Pod TPU/GPU Circuit) | | (Intra-Pod TPU/GPU Circuit) | +---------------------------------+ +---------------------------------+ ```
1. **Scale-in Domain (Orange):** High-bandwidth, ultra-low-latency fabric engineered for tightly coupled intra-pod accelerator communication (e.g., optical switching-based Inter-Chip Interconnects / ICI used in TPU pods). 2. **Scale-out Accelerator Fabric (Yellow - Virgo):** A dedicated fabric optimized for massive horizontal scaling across accelerator pods. 3. **Front-End Fabric (Jupiter):** The proven front-end network providing fast, reliable access to distributed storage, general compute resources, and the global WAN. Jupiter ensures data access doesn't bottleneck training or serving, and allows multiple AI clusters within the same building to share front-end capacity efficiently.
This architectural decoupling between front-end and back-end offers three strategic benefits: independent evolution/upgrades of each domain without systemwide disruption; maximum non-blocking bisectional bandwidth for training while optimizing front-end TCO; and tight lockstep co-design with new ML accelerator hardware.
- **Scale-in (ICI):** Intra-pod, ultra-low latency. - **Scale-out (Virgo):** Inter-pod, massive horizontal scale across pods. - **Front-end (Jupiter):** Storage, management, WAN access, cross-site cluster connection.
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[08:36](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=516s) Multi-Plane Design and Skinny Links
Zooming into the Virgo architecture details, Lee highlights how the network achieves extreme scale without adding extra topology layers:
- **Flat 2-Layer Topology:** By using high-radix switches, Virgo collapses multi-tier trees into a flat, non-blocking 2-layer topology. This drastically reduces packet transit latency by cutting the number of required switch hops. - **Skinny Links & Multi-Plane Isolation:** To maximize switch radix, logical links are configured using "skinny links" at lane speeds as low as 30 Gbps (SerDes). The number of available planes ($N$) is a function of the skinny links per accelerator. For example, a Network Interface Card (NIC) with 1.6 Tbps bandwidth using 200G/30G lane speeds provides 8 skinny links per chip, creating an 8-plane architecture. - **Graceful Degradation:** If an entire network plane fails, $N-1$ planes remain fully operational. In an 8-plane design, a single plane outage leaves 87.5% of total bandwidth available to every chip—a massive improvement over legacy architectures where a single link/switch failure could drop per-chip bandwidth by 50% to 100%. - **Scale Limits:** Multi-plane skinny-link designs allow non-blocking domains to scale $N \times$ larger without needing a 3rd switching tier. Virgo can scale up to **1,000,000 TPU/GPU chips** (specifically TPU v6e/v8-class targets) within a single logical cluster across campus sites. - **Multipath Load Balancing:** - *Switch-driven Adaptive Routing:* Extremely fast local reaction to switch failures/congestion, plus rapid downstream failure notifications. - *SRv6 Source Routing:* Supported for bare-metal customers bringing custom host networking stacks to distribute traffic evenly at packet-level granularity across all available fabric paths.
- **Bandwidth Resiliency:** 8-plane design guarantees 87.5% capacity retention during a full plane failure. - **Max Cluster Scale:** Up to 1 million accelerator chips in a single logical cluster. - **Routing Mechanisms:** Adaptive routing (hardware-level) + SRv6 (host-level packet distribution).
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[13:05](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=785s) High-Resolution Telemetry and Consolidated In-Band Congestion Signaling (CEC)
AI workloads are notorious for bulk synchronization phases, creating extreme burstiness. Because congestion and failures cause costly training interruptions, Virgo elevates telemetry to a "first-class citizen" operating in two modes:
1. **High-Resolution Streaming Telemetry:** Live switch port bandwidth utilization and metric streaming sampled at sub-millisecond intervals. 2. **Consolidated In-Band Congestion Signaling (CEC):** High-resolution congestion metrics embedded directly inside data plane packets.
Lee explains that CEC is an advanced evolution of In-Band Network Telemetry (INT)—a technology he personally worked on during his time at Barefoot Networks. Unlike standard INT, which appends per-hop metadata to the packet header (causing header bloat that can exceed the payload size over deep paths), CEC aggregates metrics across hops using `MIN` or `MAX` mathematical aggregation functions.
As a result, CEC maintains a **constant header overhead** regardless of how many hops a packet traverses, while still providing exact bottleneck location data. Supported end-to-end across Virgo switch ASICs and NICs, CEC is currently being standardized within the **Ultra Ethernet Consortium (UEC)**, with an upcoming **SIGCOMM 2026** paper detailing its design and production deployment history at Google.
- **Metric Aggregation:** Uses `MIN`/`MAX` functions to prevent packet header inflation. - **Header Overhead:** Fixed/constant size regardless of hop count. - **Standardization & Research:** Adopted by UEC; detailed in a SIGCOMM 2026 paper.
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[15:47](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=947s) Telemetry Demo: Unmasking Invisible Micro-Bursts
Lee shares a side-by-side dashboard demo illustrating why standard monitoring tools fail in AI environments:
- **Standard View (30-second averages):** The monitoring dashboard shows a healthy network with wide headroom, claiming an average port utilization of roughly 10%. - **Sub-Millisecond View:** Toggling the telemetry view to sub-millisecond resolution reveals massive green saturation spikes hitting **100% link capacity** every few seconds. - **The Finding:** 30-second—and even 100-millisecond application-level—averages completely erase micro-bursts, creating "invisible congestion" during synchronized AI workload phases. Google utilizes this sub-millisecond visibility to harden fabric control loops and tune next-generation switch hardware.
``` Standard 30s View: [--- 10% Avg Load ---] -> (Looks healthy, hides problems) Sub-millisecond View: [||| 100% SPIKE |||] -> (Redlining switches continuously) ```
- **Demo Takeaway:** Standard telemetry masks micro-bursts that destabilize collective communication routines during model training.
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[17:39](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=1059s) Future Roadmap and Industry Call to Action
Looking ahead, Lee outlines the next development frontiers for Virgo and leaves the community with key takeaways:
1. **Multi-Metro Fabric Scaling:** Expanding Virgo fabrics across data center campuses separated by hundreds or thousands of kilometers. Running high-performance RDMA over long-haul connections introduces major challenges due to multi-millisecond round-trip times (RTT). Google is collaborating with industry partners to adapt CEC for sub-RTT congestion and failure signaling. 2. **Multi-Vendor Interoperability:** A direct call to action for the networking community to standardize telemetry protocols and fast route-change notifications for adaptive routing across diverse hardware vendors.
In closing, Lee expresses how thrilling it is to be a network engineer today: technologies once considered niche or overlooked—such as In-Band Network Telemetry, CEC, adaptive routing, and data center source routing—are now being deployed globally at breakneck speed to power the AI revolution.
He concludes by displaying a QR code linking to a technical blog post co-authored with an Google Fellow and invites attendees to connect via email for future collaboration.
- **Target Expansion:** Cross-campus / multi-metro long-haul fabrics (100s to 1000s of km). - **Core Challenge:** Maintaining RDMA performance over millisecond-level RTTs. - **Industry Call:** Multi-vendor standardization around UEC, CEC, and adaptive routing protocols.
## Notable quotes > [00:41](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=41s) basically everything to break. — Jeongkeun "JK" Lee
> [08:36](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=516s) Skinny Links & Multi-Plane Isolation — Jeongkeun "JK" Lee
> [13:05](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=785s) MIN — Jeongkeun "JK" Lee
> [13:05](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=785s) MAX — Jeongkeun "JK" Lee
> [15:47](https://www.youtube.com/watch?v=00Gcgk9FJf4&t=947s) Standard 30s View: [--- 10% Avg Load ---] -> (Looks healthy, hides problems) Sub-millisecond View: [||| 100% SPIKE |||] -> (Redlining switches continuously) — Jeongkeun "JK" Lee
## Mentioned Jeongkeun "JK" Lee, Google, HP Labs, Barefoot Networks, P4, Tofino, @Scale, Jupiter, Orion, Apollo, QUIC, TCP BBR, Andromeda, gRPC, PSP, Falcon, Virgo, A5x, NVIDIA Vera Rubin NVL72, TPU, TPU v6e, TPU v8, SRv6, CEC, In-Band Network Telemetry, INT, Ultra Ethernet Consortium, UEC, SIGCOMM 2026, RDMA
[Source](https://www.youtube.com/watch?v=00Gcgk9FJf4)