@Scale
Meta is releasing its MetaRoCE RDMA transport to open standards to enable multiplane commodity Ethernet clusters and eliminate specialized switch hardware for million-GPU AI networks.
AI-assisted summary of Live from SCCC: MetaRoCE: Meta’s RDMA Transport | Arvind Srinivasan and Kingshuk Mandal — original source. Check the original for full context.
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## Background Published by @Scale on YouTube on August 31, 2026, this video features Meta's Arvind Srinivasan and Keysight's Kingshuk Mandal presenting live from the Santa Clara Convention Center. The page description outlines how MetaRoCE was created as a clean-sheet, multipath, receiver-driven RDMA transport to solve the massive networking bottlenecks of AI clusters scaling to over a million GPUs, while highlighting Meta's open-source commitment and Keysight's companion conformance suite.
## TL;DR MetaRoCE decouples transport intelligence from switch topology by pushing congestion control, dynamic packet spraying, and receiver-driven incast management directly onto endpoint NICs. Designed to achieve up to 90% fabric efficiency on commodity Ethernet without switch-level customization, it eliminates traditional Queue Pair (QP) proliferation while maintaining per-path RTT tracking and isolation. Keysight's KAI Conformance suite complements the protocol by executing day-zero validation across software, RTL emulation, and production silicon to eliminate hardware bugs like Receiver Not Ready (RNR) freezes and shared RTO shortcuts before tap-out. Ultimately, Meta is opening MetaRoCE to the broader hardware ecosystem to establish a multi-vendor, standardized transport for next-generation scale-out, scale-up, and regional AI networks.
## Atmosphere & style The presentation carries an authoritative, pragmatic, and highly technical tone tailored for an audience of network architects and infrastructure engineers. The narrative flows smoothly between Arvind Srinivasan's visionary perspective on macro-economic AI bottlenecks and Kingshuk Mandal's sharp, hands-on focus on silicon validation realities. The session feels collaborative and forward-looking, balancing high-stakes engineering challenges with a clear passion for open-source industry standards.
## Key takeaways - [00:00](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=0s) Meta introduced MetaRoCE, a clean-sheet RDMA transport protocol built to solve severe networking bottlenecks as AI clusters scale to over one million GPUs across regions. - [00:00](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=0s) Collective operations in AI workloads operate like an army marching at the speed of the slowest worker, turning network tail latency and packet drops into macroeconomic bottlenecks that risk stranding billions of dollars in compute. - [02:13](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=133s) Traditional RDMA relies on switch fabric signals (e.g., ECN) for congestion control, but switches only see raw packets whereas endpoints see workload intent. - [02:13](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=133s) MetaRoCE shifts all intelligence, load balancing, and failure management to endpoint NICs, allowing network switches to remain simple, commodity Ethernet units. - [04:09](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=249s) MetaRoCE exposes large network pipes as sets of multiple sub-paths, splitting application messages into individual packets sprayed out-of-order across distinct paths. - [04:09](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=249s) Each path maintains its own distinct entropy, congestion control state, and RTT tracking, isolating link drops or timeouts to single paths without dragging down overall performance. - [08:33](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=513s) Sender congestion control operates per-path while receiver NICs calculate fair-share bandwidth hints during incast patterns, preventing heavy all-to-all incast congestion. - [08:33](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=513s) MetaRoCE eliminates Queue Pair (QP) proliferation by handling high bandwidth through internal multi-pathing under single coordinated QPs rather than running hundreds of uncoordinated QPs. - [11:00](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=660s) To convert written specifications into interoperable hardware, Meta partnered with Keysight to build the Keysight AI Conformance (KAI Conformance) test suite for MetaRoCE v1.0. - [12:54](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=774s) Keysight's testing continuum executes identical conformance assertions across software reference models, RTL emulation platforms, and production silicon to catch logic bugs before expensive tap-outs. - [12:54](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=774s) A real-world case study on Mixture of Experts (MoE) workloads showed how automated conformance testing identified a DUT NIC bug where a flow failed to resume transmission after a Receiver Not Ready (RNR) timeout. - [17:10](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1030s) Sharing a single RTO timer across a Queue Pair is a tempting implementation shortcut that invalidates multipathing; per-path RTO isolation is strictly required so one congested path does not poison healthy ones. - [19:34](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1174s) Day-zero protocol conformance prevents hardware bugs from freezing into physical silicon and transforms vendor-specific private implementations into an open multi-vendor ecosystem. - [20:50](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1250s) Meta is open-sourcing MetaRoCE to the industry and expanding its transport principles beyond scale-out networks into intra-rack scale-up domains and cross-region networks.
## Detailed walkthrough ### [00:00](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=0s) Rethinking RDMA for the AI Era: Scaling to Millions of GPUs
Arvind Srinivasan from Meta opens the presentation live at the Santa Clara Convention Center by introducing **MetaRoCE**, Meta's clean-sheet RDMA transport protocol purpose-built for AI networking at scale. Setting the stage after an introduction by Ju, Arvind outlines the talk's roadmap: breaking down the scaling challenges faced in modern AI clusters, exploring MetaRoCE’s core mechanisms, demonstrating compliance and interoperability with Keysight's Kingshuk Mandal, and presenting Meta’s vision for an open industry ecosystem.
As Meta scales its infrastructure from thousands of GPUs to clusters exceeding one million accelerators spanning data halls, data centers, and entire regions, the underlying network infrastructure must expand at an identical exponential pace. Connecting a million accelerators translates to needing "trillions of wires," shifting the network from an auxiliary background component into the primary bottleneck that determines whether a million GPUs can actually function together.
In AI workloads, network performance is directly tied to job execution speed. Arvind highlights a critical physical reality: collective operations act "like an army marching," where the entire formation moves strictly at the pace of the slowest soldier. Any microsecond of tail latency or packet drop directly translates to billions of dollars in stranded compute time. Resiliency and tail latency cease to be purely technical networking problems—they become macro-economic imperatives for AI infrastructure.
- **Scale Target:** Expanding beyond 1,000,000 GPUs across data halls, data centers, and multi-region deployments. - **Interconnect Demand:** Exponential 10x growth in connected accelerators over short time horizons. - **Economic Impact:** Gated performance on collective operations directly risks stranding billions of dollars of GPU compute.
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[02:13](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=133s) Shifting Intelligence from Fabric to Edge
Taking a historical step back, traditional RDMA (RoCE) has been the workhorse of high-performance computing (HPC) for decades. However, as cluster sizes scaled into tens of thousands of nodes, traditional RDMA transport models began to break down, creating persistent hotspots, burst storms, and severe fabric underutilization. Up until now, the industry worked around these limits by passing workload "hints" down into the network switches, hoping the switch fabric could resolve congestion. This resulted in constant operational firefighting and fragile tuning.
Arvind pinpoints the fundamental structural flaw of traditional architectures: *the network fabric only sees raw packets, whereas only the NIC and endpoints see the actual workload intent*. By moving intelligence out of the fabric and pushing it entirely to the endpoint NICs, the edge can perform intelligent load balancing directly across the network. If the NIC possesses granular per-path visibility, it can drive aggregate performance, manage resiliency, and handle load balancing without requiring the underlying network switches to be smart.
This edge-driven approach unlocks cost-optimized network topologies, such as multi-plane, free-pass-fabric (FPF) architectures. By decoupling transport intelligence from fabric topology, Meta shifts the burden of congestion and failure management entirely to smart edge nodes, allowing the network fabric to remain simple, commodity, and scalable.
- **Traditional Fallback:** Over-reliance on switch fabric intelligence via coarse-grained signals (e.g., ECN, CNP) leads to persistent congestion and burst storms. - **Architectural Shift:** Pushing flow intent and load balancing to the endpoint NIC decouples transport logic from switch topology. - **Topology Benefit:** Enables cost-effective multi-plane Ethernet topologies without requiring specialized switch hardware.
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[04:09](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=249s) MetaRoCE Core Architecture: Multipath and Per-Path Intelligence
Traditionally, applications view the network as a single, opaque, "big fat pipe" with zero visibility into internal network dynamics. MetaRoCE replaces this model by exposing the large network fabric to the transport layer as a set of multiple "tiny pipes," enabling fine-grained, intelligent routing decisions that remain completely transparent to the user application. MetaRoCE is designed around three primary dimensions of scale:
1. **Performance at Scale:** Achieves up to 90% fabric efficiency using per-packet load balancing and dynamic multipathing. 2. **Resiliency:** Provides per-path reliability and fast fault recovery without requiring any switch-level intervention. 3. **Operations at Scale:** Built on standard commodity Ethernet with full Verbs API compatibility, ensuring frictionless adoption for existing AI applications without needing specialized switches.
At the heart of MetaRoCE is the abstraction of a **path**. Rather than pinning a Queue Pair (QP) to a single network flow—which causes massive elephant flows and fabric hot-spotting—MetaRoCE splits application messages into individual packets and sprays them across multiple independent paths. At the receiving end, packets are reassembled directly into the receiver's memory buffer regardless of the underlying RDMA operation semantics.
Each path is assigned a distinct entropy value managed automatically by the transport. Crucially, every individual path maintains its own independent congestion control state and round-trip time (RTT) tracking. This design allows MetaRoCE to scale naturally across non-uniform RTT topologies. Load balancing decisions adapt dynamically based on real-time RTT measurements and available window sizes, allowing the NIC to bypass network hotspots. If a path times out or experiences link flaps, MetaRoCE automatically rotates path entropies to find an unmanaged route, isolating failures so one degraded path never drags down the performance of others.
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[08:33](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=513s) Sender Congestion Control, Receiver Incast Control, and Avoiding QP Proliferation
MetaRoCE features a unique dual-ended congestion control scheme designed to handle heavy AI workloads without switch customization:
- **Sender-Driven Per-Path Congestion Control:** Congestion response (such as Additive Increase/Multiplicative Decrease) is evaluated strictly on a per-path basis. If an Explicit Congestion Notification (ECN) or loss occurs on one specific path, only that single path throttles its rate. The total window available to the Queue Pair is the aggregate sum of all active path windows. Adding more paths increases available bandwidth capacity without increasing transport aggressiveness. - **Receiver-Driven Rate Hints for Incast:** To prevent many-to-one incast bottlenecks (common in all-to-all collective patterns), the receiving NIC calculates fair-share bandwidth limits based on the number of active incoming senders. The receiver transmits rate hints back to senders inside ACK packets, allowing endpoints to manage incast bandwidth distribution dynamically without relying on switch buffer management. - **Elimination of QP Proliferation:** Traditional implementations attempt to scale bandwidth by multiplying the number of Queue Pairs (QPs) per host. At scale, hundreds of uncoordinated QPs run competing congestion algorithms, stepping on each other and degrading aggregate throughput. MetaRoCE solves this by maintaining a low QP count and scaling bandwidth through internal multi-pathing managed by a single coordinated transport engine.
Meta's core goal is to run high-density GPU workloads across heterogeneous, commodity Ethernet networks using standard ECN and ECMP mechanisms—avoiding proprietary vendor lock-in or specialized hardware extensions.
- **Efficiency Metric:** Targets 90% network utilization via packet spraying and per-path dynamic routing. - **Commodity Support:** Requires only basic ECN (Explicit Congestion Notification) and ECMP (Equal-Cost Multi-Path) from underlying switches. - **QP Management:** Replaces uncoordinated multi-QP bandwidth scaling with coordinated multi-pathing under single QPs.
---
[11:00](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=660s) Open Standards and Keysight Compliance Framework
To ensure MetaRoCE becomes a ubiquitous industry transport rather than an isolated proprietary technology, Meta is opening the protocol specification to the broader AI ecosystem. Arvind emphasizes that "interoperability is just a spec" until validated by a robust compliance suite. To turn written specifications into interoperable hardware, Meta partnered with Keysight Technologies.
Kingshuk Mandal from Keysight takes the stage to explain how protocol compliance bridges the gap between written standards and real-world silicon:
> "A protocol specification becomes an interoperable system when multiple vendors agree on the wire. Until then, one implementation talking to itself is a private implementation... Specification is written words, and conformance converts these written words into testable assertions."
Kingshuk underscores the harsh economic reality of hardware design: **silicon is brutally expensive to patch**. Any ambiguity left in a transport specification that slips past tap-out gets permanently frozen into the physical chip, costing millions in respin expenses. To avoid post-mortems, Keysight developed the **Keysight AI Conformance (KAI Conformance)** test suite for MetaRoCE v1.0, executing test plans from day one against reference software models, RTL emulation platforms, and final production silicon.
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[12:54](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=774s) Testing in Continuum and Real-World Case Study: Receiver Not Ready (RNR)
Keysight’s testing framework operates as a continuous pipeline. The exact same protocol test cases, workflow, and pass/fail quality bars are applied across every stage of the hardware lifecycle:
``` [ Software Reference Implementation ] ➔ [ RTL Emulation ] ➔ [ Production Silicon ] ```
Because the pass/fail bar never moves, bugs discovered during architecture prototyping are resolved via simple code updates rather than multi-million-dollar post-tapout silicon respins. The test suite aggressively probes corner-case paths, including negative acknowledgements (NACKs), timer roll-overs, and recovery states where production bugs typically hide.
Kingshuk walks through a real-world case study involving **Mixture of Experts (MoE)** workloads. In MoE model training, thousands of GPUs engage in massive all-to-all communication phases. Occasionally, a target machine temporarily runs out of memory buffer space to accept incoming transfers. This non-error condition is signaled via an **RNR (Receiver Not Ready)** frame, where the receiver politely requests the sender to pause and retry after a backoff duration.
In MetaRoCE's multipath architecture, a single Queue Pair may handle multiple active flows using distinct packet tags (entropies). The MetaRoCE specification explicitly mandates that upon receiving an RNR for a specific tag, the sender NIC **must pause only the impacted tag and its associated message**, while allowing all other tags and flows on that same QP to continue transmitting normally.
During early conformance testing on a Device Under Test (DUT) NIC acting as a sender: - The Keysight test tool emulated an RNR response targeting a single specific tag. - **The Bug:** The DUT NIC correctly paused the impacted tag, but due to a logic flaw, **forgot to wake up after the timeout expired**, leaving that specific flow permanently frozen. - **The Takeaway:** Conformance tools allow vendors to deterministically trigger and validate subtle recovery bugs on demand before freezing RTL design files.
- **Conformance Suite:** Keysight AI Conformance (KAI Conformance) suite built specifically for MetaRoCE 1.0. - **Coverage Scope:** Full domain coverage including hardware header integrity, per-path congestion, reliability timeouts, NACK handling, and edge recovery. - **Target Workloads:** Validates dynamic behavior under heavy MoE (Mixture of Experts) and all-to-all traffic stress patterns.
[17:10](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1030s) Validating Independent Path RTO: Testing the Single Most Tempting Shortcut
Kingshuk Mandal demonstrates how Keysight tests device-under-test (DUT) path isolation in MetaRoCE. Because MetaRoCE sprays packets across multiple paths and tracks each path individually, maintaining an independent Retransmission Timeout (RTO) for every single path is critical. In simple terms, RTO is the timer used by the sender to determine when a packet has been dropped so it can retransmit. Managing RTO involves a delicate balance: setting it too small floods the network with redundant duplicates and collapses goodput, while setting it extra large causes flows to stall excessively, degrading Job Completion Time (JCT).
The MetaRoCE specification explicitly mandates that each path maintain its own independent RTO. However, Kingshuk points out that adapting a single, shared RTO for the entire Queue Pair (QP) is "the single most tempting shortcut in the whole design." While sharing a single RTO requires much less memory, fewer lines of code, and is genuinely simpler to implement, it is fundamentally wrong. To catch this flaw, Keysight configures a test topology featuring multiple paths between the DUT and the emulation tool: * **Path 0:** Deliberately maintained as a fast, healthy, high-speed path expected to achieve a very low RTO floor. * **Path 1:** Intentionally injected with heavy congestion to force a high RTO.
In a correct NIC implementation, Path 0 settles down to its fast baseline, while Path 1 scales up its RTO to absorb local delays—yielding a pass. But if an implementation takes the shortcut of a shared QP RTO, the single congested path drags down all healthy ones. "One unhealthy path is going to poison the entire good set," Kingshuk warns. "The moment that happened, you have already thrown away multipath. You have paid for eight individual lanes, but you are driving all of them at the speed of the one that is jammed." While every path stays healthy in a sanitized lab environment, this flaw manifests in real-world deployments as "a mysterious latency coupling multiple paths under load"—a nightmare bug that can take weeks to debug.
[19:34](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1174s) Why Day-Zero Conformance Turns a Draft into a Vibrant Ecosystem
Kingshuk shifts focus to the strategic necessity of validating transport protocol specifications early in the development lifecycle. A brand-new transport technology like MetaRoCE cannot be treated as something tested at the tail end of hardware development. Ambiguity left in the specification while silicon freezes gets permanently etched into the die, and "hardware is brutally expensive to patch."
Day-zero conformance pays off for all three major industry stakeholders simultaneously: * **Protocol & ASIC Designers:** Catch specification ambiguities early while silicon designs are still editable, hardening the protocol bit for bit. * **Network Architects:** Guarantee a true multipath network that handles degradation gracefully with proper isolation and recovery, verified under stress and fault injection rather than just the happy path. * **Fabric Operators:** Uncover subtle edge-case bugs that typically surface only under live production workloads long before deployment.
Kingshuk emphasizes that a protocol implemented by a single vendor remains nothing more than a private implementation. Rigorous, open conformance from day zero turns a specification draft into a vibrant, multi-vendor ecosystem.
[20:50](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1250s) Expanding MetaRoCE: Million-GPU Fabrics and Open Collaboration
Arvind Srinivasan returns to conclude the presentation with Meta's vision for future AI scale. Tomorrow's network demands are unprecedented, as Meta builds million-GPU clusters designed to solve "trillion-wire connectivity across millions of ASICs." MetaRoCE achieves peak AI workload performance and high availability on commodity Ethernet without requiring specialized switches or locking operators into proprietary hardware ecosystems.
Meta is opening MetaRoCE to the broader industry and empowering the NIC vendor ecosystem to build compliant silicon. Later in the conference schedule, representatives from AMD (Sep and Bali) present their own native implementation of MetaRoCE on AMD hardware platforms. Arvind concludes by stressing that Meta's networking team is far from done: * **Current Expansion Focus:** Extending MetaRoCE principles beyond scale-out fabrics to tackle intra-rack scale-up domains as well as cross-region front-end networks. * **Call to Action:** Every layer of the AI network stack demands a fundamental rethinking, inviting industry partners to collaborate on open transport standards.
---
<ElicitationsGroup message="Explore related aspects of MetaRoCE architecture and test methodologies:"> <Elicitation label="Deep dive into MetaRoCE multipath & packet-spraying design" query="Can you explain the detailed packet-spraying mechanisms and out-of-order handling used by MetaRoCE?"/> <Elicitation label="Overview of Keysight's network emulation suite" query="How does Keysight's validation and emulation suite test RDMA transport protocols under lossy network conditions?"/> </ElicitationsGroup>
## Notable quotes > [00:00](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=0s) like an army marching — Arvind Srinivasan
> [02:13](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=133s) the network fabric only sees raw packets, whereas only the NIC and endpoints see the actual workload intent — Arvind Srinivasan
> [11:00](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=660s) A protocol specification becomes an interoperable system when multiple vendors agree on the wire. Until then, one implementation talking to itself is a private implementation... Specification is written words, and conformance converts these written words into testable assertions. — Kingshuk Mandal
> [11:00](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=660s) silicon is brutally expensive to patch — Kingshuk Mandal
> [12:54](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=774s) must pause only the impacted tag and its associated message
> [12:54](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=774s) forgot to wake up after the timeout expired
> [17:10](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1030s) the single most tempting shortcut in the whole design — Kingshuk Mandal
> [17:10](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1030s) One unhealthy path is going to poison the entire good set — Kingshuk Mandal
> [17:10](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1030s) You have paid for eight individual lanes, but you are driving all of them at the speed of the one that is jammed. — Kingshuk Mandal
> [17:10](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1030s) a mysterious latency coupling multiple paths under load — Kingshuk Mandal
> [19:34](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1174s) hardware is brutally expensive to patch — Kingshuk Mandal
> [20:50](https://www.youtube.com/watch?v=QX8C-8uxXKc&t=1250s) trillion-wire connectivity across millions of ASICs — Arvind Srinivasan
## Mentioned Arvind Srinivasan, Kingshuk Mandal, Ju, Sep, Bali, Meta, Keysight Technologies, AMD, @Scale, Santa Clara Convention Center, MetaRoCE, RDMA, RoCE, Ethernet, Keysight AI Conformance (KAI Conformance), Verbs API
[Source](https://www.youtube.com/watch?v=QX8C-8uxXKc)