What will computer chips look like in 2045?

2045年的计算机芯片会是什么样？ 本期内容探讨了塑造未来二十年半导体制造的技术前沿与物理瓶颈。面对AI工作负载中严峻的数据传输瓶颈，半导体行业正从传统封装转向亚微米间距的直接混合键合，这模糊了封装与原生片上互连之间的界限。然而，前沿晶圆厂的扩产面临严苛的物理限制：全球设备供应无法支持10倍的规模扩张，且长达18个月的设备交付周期将任何新建晶圆厂的投产推迟至2030年左右。英特尔高管讨论了如何依靠良率可预测性而非单纯的资本支出与台积电竞争、在AI热潮前夕剥离存储业务的阵痛，以及像埃隆·马斯克的“Terafab”这样旨在彻底重塑天文数字级建厂成本的激进尝试。 全球半导体设备制造能力将前沿晶圆厂的产能扩张限制在约2倍左右，导致该行业在物理上无法支撑AI算力需求每年3倍的增长率。 (50:00) 随着直接混合键合技术迈向亚0.5微米间距，先进封装正在实质性地融入片上互连层，通过消除焊料微凸块大幅降低接口功耗。 (45:00) 半导体设备约18个月的交付周期加上晶圆厂的建设周期，意味着如今启动建设的任何全新晶圆厂产能，都要到2028至2030年才能实现量产。 (60:00) 极高的资本密集度已使先进制程半导体制造整合至仅剩三家企业——台积电、英特尔和三星，其中台积电的年度资本支出约为500亿美元，远超英特尔的约200亿美元。 (56:45)

## Background 该内容由 Dwarkesh Patel 于 2026 年 10 月 22 日发布在其同名播客与网站上。节目基于他在英特尔晶圆厂进行为期两天的实地探访与高管深度访谈，旨在探讨在过去十年 AI 算力需求每年增长 3 倍的背景下，全环绕栅极（GAA）、背面供电、CFET、混合键合等前沿制程创新将如何塑造未来计算机芯片的形态与物理极限。 ## TL;DR 节目深入剖析了半导体工艺从平面晶体管走向 GAA 及未来垂直堆叠 CFET 的技术演进，并详细复盘了英特尔从 10nm 激进缩放挫折中吸取的“阶段门禁”教训。访谈揭示了英特尔采用背面供电与单次曝光 High-NA EUV，而台积电选择按兵不动的底层架构分歧，并探讨了钌替代铜互连与亚微米混合键合封装的最新进展。英特尔首席技术官坦言，受制于 ASML 等关键设备厂商的物理产能天花板，全球先进制程总产能到 2030 年前仅能翻倍而无法实现 10 倍扩张；面对动辄数百亿美元建厂成本所带来的极度风险厌恶，英特尔正全力提升代工执行力并加速锁定关键制造工具以追赶台积电。 ## Atmosphere & style 对话充满硬核工业实证与严谨的技术交锋，Dwarkesh 尖锐直接的追问与英特尔一线研发主管、CTO 的坦率回应形成了张力十足的现场感。访谈既有深入纳米级电镜与无尘室机台排障的微观工程细节，又有对百亿美元 CapEx 豪赌与半导体地缘格局的宏观审视。整体氛围理性克制中透露着面对物理极限与产能死局的现实清醒，给听众带来一种沉浸式穿透万亿美元芯片制造黑盒的震撼体验。 ## Bulletin - `50:00` 过去十年 AI 算力需求每年激增 3 倍，但全球关键半导体设备产能受限，短期内先进制程晶圆产出最多仅能翻倍，难以支撑 10 倍级别的产能扩张。 - `13:13` 英特尔 14A 节点部署单价约 4 亿美元的 High-NA EUV 光刻机，依托背面供电技术实现单次曝光直写，而台积电因正面布线过密仍需多重曝光，认为该机台在当前缺乏经济性。 - `53:14` 晶圆制造的固定成本占比高达约 80%，极端的规模经济壁垒使得全球先进制程玩家在过去四十年间从 20 余家缩减至仅存的台积电、英特尔与三星三巨头。 - `30:00` 芯片微缩正触及物理极限，互连层在约 20 纳米节距以下正探索免衬层的钌替代铜，晶体管架构则从全环绕栅极（GAA）迈向上下垂直堆叠 NMOS 与 PMOS 的互补场效应晶体管（CFET）。 ## Key takeaways - `00:00` AI 算力爆发引发巨大的先进制程产能缺口，但设备供应受制于 ASML 光刻机等核心机台的产能上限，无法通过单纯堆砌资本在短期内实现数倍扩张。 - `03:22` 英特尔汲取了 10nm 节点激进推行“超大规模缩放”导致延期四年的教训，重构了技术研发流程，引入包含硬性良率和缺陷指标的“阶段门禁”机制以保交付进度。 - `06:28` 晶体管架构经历了从二维平面、三面包裹的 FinFET 到四面环绕的 GAA（RibbonFET）的演进，核心目标是在微观物理极限下彻底遏制短沟道漏电流。 - `13:13` 底层芯片架构直接决定光刻机的经济性：英特尔依靠背面供电（PowerVia）释放了正面布线空间，使 High-NA EUV 能单次曝光成型，而台积电沿用传统布线则面临多重曝光的成本与缺陷惩罚。 - `15:00` 英特尔在从自研自产的 IDM 转向晶圆代工模式的过程中面临陡峭的学习曲线，曾因缺乏行业标准化的商业级 PDK 而导致外部客户适配受阻。 - `23:33` 晶圆厂内部通过 Hotbox 优先级通道加速关键实验，集成工程决策必须在数据不完全的情况下快速权衡商业风险与投产时间表。 - `30:00` 当金属互连线缩减至 20 纳米节距以下时，铜导线所需的高阻抗衬层严重挤占导电截面积，具备直接干法刻蚀能力的金属钌成为替代铜的前沿候选材料。 - `32:41` CFET 将 NMOS 与 PMOS 进行垂直堆叠以在理论上翻倍晶体管密度，但面临极端高深宽比刻蚀、无气隙填充困难以及严峻的散热挑战，距离商业量产仍需多年探索。 - `40:00` 算力瓶颈正在从单晶片计算演变为芯片间通信的“面积 vs 周长”瓶颈，去除焊球的铜对铜混合键合（Hybrid Bonding）将互连间距缩小至亚微米级，显著提升带宽并降低互连能耗。 - `50:00` 超大规模云厂商（Hyperscalers）自研芯片并大举包揽整座晶圆厂产能，推动半导体产业从水平分工形态重新走向“伪垂直整合”。 - `53:14` 先进制程代工的固定成本高达 80%，产能利用率和良率的微小提升能够带来非线性的巨额利润，极端的规模效应驱动了半导体制造行业的持续高度洗牌。 - `55:00` 英特尔认为其先进制程底层技术已基本追平台积电，代工争夺的核心焦点在于高吞吐量下的良率爬坡、准时交付等代工执行力以及完善的器件生态库。 - `01:00:00` 从下单采购关键光刻设备到新晶圆厂建筑外壳完工投产至少需要 18 个月到数年时间，这一物理建造周期锁死了 2030 年前全球先进芯片产能的绝对上限。 - `01:01:02` 单座先进制程晶圆厂造价及 High-NA 光刻设备成本的指数级攀升，使行业陷入极度厌恶风险的范式僵局，迫使业界反思对极端洁净室与传统制造教条的依赖。 ## Detailed walkthrough ### `00:00` AI 算力海啸与芯片制造的物理极限 半导体行业正在经历前所未有的外部冲击。随着人工智能对算力需求的爆炸式激增，先进制程代工厂正面临前所未有的产能缺口。正如业内人士所言：“AI 正在驱动令人难以置信的计算需求，轻松高出我们最大产能的 40% 到 50%，这是我此前从未见过的。”过去十年间，AI 算力需求以每年翻三倍的速度递增，为了维持这一趋势，像英特尔这样的芯片代工厂不仅需要大幅提升单颗芯片的计算能力，更要制造出海量的先进制程晶圆。 然而，芯片产能的扩张严重依赖供应链设备的交付，其中最关键的就是阿斯麦（ASML）的极紫外光刻机（EUV）。如果设备供应无法跟上，“没有设备，他们就无法在这里制造芯片”。为了摸清尖端芯片制造的全流程以及底层硬件如何塑造 AI 的未来，Dwarkesh Patel 深入英特尔晶圆厂进行了为期两天的探访，采访了英特尔制程开发主管克里斯·奥斯（Chris Auth），试图还原尖端制程节点落地的真实复杂性。 ### `00:47` 揭秘英特尔制程研发：14A 节点与两千道工序的良率攻坚 英特尔目前正在研发代号为“14A”的下一代尖端工艺节点。虽然距其推向市场可能还有两到三年时间，但事实上 14A 已经在前期研发中推进了三年有余。目前该节点正处于敲定制程方案、锁定制造机台工具集（Tool sets）并对每个微小步骤进行精细微调的收尾冲刺阶段。在芯片制造工厂中，一片晶圆从开始到完成大约需要经过整整 2,000 道工艺步骤，每一步都必须做到极致精细，以确保每周能稳定量产数千片晶圆，并保证每一次生产都具备高度的可重复性。 在解答良率如何按月稳步提升的问题时，Chris Auth 详细解释了这一闭环排查体系： ```mermaid flowchart TD accTitle: 晶圆缺陷检测与良率排查流程 accDescr: 展示英特尔通过在线量测与后道测试发现缺陷并结合TEM分析定位工艺步骤的闭环流程 subgraph INLINE["在线监测与终端测试"] A["在线量测 (Inline Metrology)<br/>监控晶圆表面缺陷"] B["后道测试 (End of Line)<br/>电学测试与晶圆分选"] end subgraph LAB["实验室物理分析"] C["透射电镜实验室 (TEM Lab)<br/>对缺陷部位制作微观横截面"] D["物理定位<br/>确认缺陷所在层级与结构"] end subgraph FIX["根因锁定与工艺调整"] E["关联工艺流段<br/>锁定产生缺陷的工序与机台"] F["工艺精细微调<br/>消除缺陷并提升良率"] end A --> C B --> C C --> D D --> E E --> F F -.->|"持续迭代"| A ``` - **在线量测（Inline Metrology）**：在晶圆加工流转的各道工序间，检测机台会实时扫描晶圆表面，直接标记出“这里有一个缺陷、那里有一个缺陷”。 - **后道电学测试与分选（End of Line Test & Sort）**：当晶圆走完整个流程后，通过电学性能测试寻找失效单元，汇总失败分布图。 - **失效分析与透射电子显微镜（TEM）截面观测**：失效晶圆会被送往透射电镜实验室，工程师切出纳米级横截面，精确观察缺陷卡在哪些金属层或介质层之间。 - **工艺流溯源与闭环解决**：一旦明确了缺陷的物理层级，工程师就能将其与特定工序段的在线量测数据进行比对，锁定产生缺陷的机台和化学步骤，进而针对性攻关修复。 ### `03:22` 10nm 节点的惨痛教训与“阶段门禁”机制 在追求先进制程的过程中，英特尔曾付出过沉重的代价。按照摩尔定律的历史节奏，英特尔原本保持着每两年推出一个全新制程节点的节拍。然而，英特尔的 10nm 节点原定于 2016 年量产，却一路延期至 2018 年才勉强投产，产品大规模出货甚至推迟了近四年，引发了市场的剧烈震荡，公司股价单日跌幅曾超 15%，而竞争对手台积电的市值则借机水涨船高。 谈及 10nm 留下的深刻教训，Chris Auth 坦言，核心问题在于当时英特尔推行了所谓的“超大规模缩放”（Hyperscaling），技术目标过于激进： > “我认为我们学到的一点是，你不能在一个制程节点里塞进太多的技术创新。因为你引入的创新越多，系统就会变得越复杂。虽然你最终确实能把它做出来，但你必须赶上特定的交付进度，而那个进度才是客户最终想要的。因此，保持可预测的时间表是一个关键要素。” 在定义 10nm 时，英特尔评估认为 ASML 的极紫外光刻（EUV）技术尚未成熟，于是试图利用现有机台和多重曝光等复杂工艺去强行实现极高的晶体管密度，这给整个工艺流程和工程师团队带来了不可承受的沉重负担。相比之下，台积电采取了更明智的节奏：在 2019 年将 EUV 投入规模量产，并在 2020 年的 5nm 节点全面铺开；而英特尔直到 2023 年才在实际产品中应用第一代 EUV 工艺，导致台积电在 EUV 机台的使用与工程经验上积累了约四年的领先优势。 为了避免重蹈覆辙，英特尔重构了技术研发流程，建立了严格的“阶段门禁”（Phase Gate）管理机制： - 技术从前沿探索（Pathfinding）转向实质开发（Development）必须通过一系列定量的成熟度指标考核。 - 门禁指标涵盖明确的**良率门槛**、**缺陷密度指标**以及**性能达标数据**。 - 如果某项新技术未能在既定节点前达到指标，它就会被果断剔除并顺延至下一代工艺，工程团队仅聚焦于当下已经完全成熟可控的技术，确保主线制程按时交付。 ### `06:28` 晶体管的演进：从平面 MOS 到全环绕栅极（GAA） 芯片性能跨越的核心驱动力，是晶体管结构从二维平面向三维立体持续演化。晶体管的本质是一个电控开关：它拥有两个端点——源极（Source）和漏极（Drain），其间的硅基底上方坐落着栅极（Gate）。当向栅极施加正电压时，静电引力会将下方硅中的负电荷（电子）向上吸引；栅极下方的一层超薄绝缘层阻止电子直接接触栅极，使得电子聚集在绝缘层下方，形成连通源极与漏极的超薄导电通路，即“沟道”（Channel），此时开关导通。当移除电压时，电子散开，沟道消失，开关关闭。 ```mermaid flowchart LR accTitle: 晶体管架构演进历程 accDescr: 从1960年的平面晶体管到FinFET再到全环绕栅极纳米片的静电控制演变 subgraph PLANAR["1. 平面晶体管 (Planar)"] direction TB P1["栅极仅覆盖沟道顶面"] --> P2["单面控制能力弱<br/>缩小时漏电严重"] end subgraph FINFET["2. 鳍式场效应晶体管 (FinFET)"] direction TB F1["硅沟道挤压成竖立垂直鳍片"] --> F2["栅极跨过鳍片包裹三面<br/>静电控制显著增强"] end subgraph GAA["3. 全环绕栅极 (Gate-All-Around)"] direction TB G1["沟道被切成多条悬空纳米片"] --> G2["栅极完全包裹纳米片四面<br/>彻底封锁微观漏电流"] end PLANAR -->|"物理极限推动"| FINFET FINFET -->|"短沟道效应驱动"| GAA ``` 随着制程不断微缩，源极与漏极的间距逼近微观物理极限，即便在开关应当关闭的断开状态下，电流也会直接穿透短沟道发生微观漏电。为了重新掌握对沟道的控制权，半导体行业逐步改变了栅极的几何包裹方式： - **平面晶体管（Planar MOSFET）**：起源于 1960 年，栅极仅单面接触沟道的顶端，在尺寸极度缩小后失去对电流的束缚能力。 - **鳍式晶体管（FinFET）**：将硅沟道拉伸、挤压成一片极其细薄的垂直“鱼鳍”，栅极像马鞍一样跨骑在鳍片上，实现从顶面和两个侧面共**三个方向**对沟道进行静电包裹。 - **全环绕栅极晶体管（Gate-All-Around / GAA，英特尔称 RibbonFET）**：将垂直鳍片水平横切成多条漂浮在半空中的超薄纳米片（Ribbons），栅极金属完全环绕并包裹每一条纳米片的**四个表面**，从而最大程度遏制漏电。 全环绕栅极（GAA）的制造难度极高，需要引入全新材料与极端复杂的替换工艺： - **交替沉积与牺牲层占位**：在硅片上交替沉积纳米级硅薄层与临时占位材料（牺牲层），形成多层“三明治”夹心结构。之所以必须使用临时占位物，是因为最终真实的金属栅极材料无法承受后续高达约 1000 摄氏度的高温烘烤工艺。 - **选择性刻蚀形成悬空纳米片**：在经历所有高温工序后，工程师使用特定的化学刻蚀剂精准掏空占位材料，使极其脆弱的单晶硅纳米片凭空悬浮。 - **高介电常数（High-k）绝缘层与金属栅极填充**：在悬空的硅纳米片周围均匀涂覆一层极薄的 High-k 绝缘材料以增强电场吸附力，随后在纳米片周围的狭窄空隙中填充真实的栅极金属，完成对沟道的 360 度全包围。 令人深思的是历史技术落地的周期：FinFET 最早于 1989 年在实验室被论证，英特尔直到 2011 年才将其推向商业化量产；而 GAA 的雏形概念早在更早的 1988 年就已被提出，但直到 2022 年三星才率先在其制程中尝试量产，前后相隔了整整三四十年。实验室原型与大规模量产之间横亘着巨大的工程与材料学鸿沟。 ### `10:00` 从登纳德缩放定律到全环绕栅极与创新的黄金时代 在 20 世纪 90 年代，半导体行业就已经知晓全环绕栅极（Gate-All-Around，GAA）晶体管的概念，但当时的核心阻碍在于如何将其引入高吞吐量的大规模制造（HVM）。研发团队必须在各种技术路径间权衡优先级，例如应变硅（Strained Silicon）、高介电常数金属栅极（High-k Metal Gate，HKMG）和 FinFET（鳍式场效应晶体管）。工程师不会在没有迫切需求时去啃最难啃的骨头，只要现有手段还能继续榨取性能，就会先推进这些技术。英特尔顺着这一逻辑，先后落地了应变硅、HKMG 和 FinFET；直到这些手段用尽，才正式回头攻坚 GAA，并着手解决如何将 HKMG 与 GAA 结构相融合的工艺挑战。这种攻坚不仅需要摸索新材料，往往还需要半导体设备厂商专门研发新机台或特种工艺气体，并经历漫长的假设验证与试错迭代。 谈及研发范式的演进，早期的微电子研发与当下截然不同。在 20 世纪 80 和 90 年代，研发主要依托登纳德缩放定律（Denard Scaling）和光刻工艺的自然演化：只要按部就班把尺寸缩小，晶体管就会变得更快、更可靠，产品路线具有极高的可预测性。但步入 2000 年代后，仅凭等比例缩小已难以为继，行业不得不迈进一个被英特尔工程师称为“创新的黄金时代”的阶段。为了维持性能与密度的提升，工艺中引入的化学元素和材料种类相比 90 年代激增了近 10 倍，原子层沉积（ALD）等原子级控制技术成为了标配。 研发哲学的转变极其剧烈：过去的研发核心是“尽量不要改变既有的工艺流程”，只需按比例缩小；现在的研发则是大刀阔斧推翻重来。正如英特尔受访工程师所描述的那种转变：“现在的做法就像是‘拿起大锤把原来的东西彻底砸碎，然后拿出全新的构想’（To now, it's like take the sledgehammer and start just tearing the thing up and come up with some new idea）。” - **工艺材料激增**：当前先进节点使用的材料种类较 1990 年代提升了大约 10 倍。 - **技术推进脉络**：等比例缩小平面晶体管 $\rightarrow$ 应变硅 $\rightarrow$ HKMG $\rightarrow$ FinFET $\rightarrow$ 全环绕栅极（GAA）及背面供电（Backside Power）。 --- ### `13:13` 高数值孔径 EUV 的经济账：英特尔为何买单而台积电按兵不动 面向 14A 节点，英特尔开始部署高数值孔径极紫外光刻机（High-NA EUV）。高 NA EUV 与现有 EUV 使用波长相同的极紫外光，但光刻机的光学系统进行了颠覆性重构。数值孔径（NA）是衡量透镜反射镜系统聚光锥角宽度的指标：光锥角度越大，在晶圆上汇聚的光斑就越细微。标准 EUV 设备的 NA 为 0.33，而 High-NA 提升至 0.55，能够在单次曝光中将可打印的特征尺寸缩小 1.7 倍。如果目标图形过小超出了机台极限，晶圆代工厂就必须采用多重曝光（Multi-patterning），使用两道、三道甚至四道曝光来拼接图案。由于一台标准 EUV 售价约 2 亿美元，多重曝光不仅极其耗时，还会显著增加良率缺陷风险。High-NA 机台价格约为标准版机台的两倍，其经济性完全取决于它能否省下足够多的曝光步骤和缺陷成本。 ```mermaid flowchart TD accTitle: EUV 光刻路径与晶圆背部架构决策对比 accDescr: 对比英特尔与台积电在晶圆互连设计与光刻技术路径上的差异 subgraph Intel["英特尔 14A 架构决策"] A1["采用背面供电 (PowerVia)"] --> A2["正面仅保留信号线，线距宽松"] A2 --> A3["High-NA EUV 单次曝光直写"] A3 --> A4["设备贵 2 倍，但节省多次曝光成本与缺陷风险"] end subgraph TSMC["台积电竞争路径"] B1["传统正面供电架构"] --> B2["正面供电+信号混合，线距极密"] B2 --> B3["线距过窄，High-NA 依然需要多次曝光"] B3 --> B4["采用标准 EUV (0.33 NA) 多重曝光，High-NA 缺乏经济效益"] end ``` 台积电公开表态 High-NA 目前并不具备经济效益，英特尔却在 14A 节点全速引入。两者针对同一款设备得出完全相反的结论，根源在于技术底层架构的差异。英特尔引入了背面供电技术（Backside Power），将原先在晶体管正面争抢空间的电源布线挪到了晶圆背面，正面仅保留信号线路。正面走线空间被大幅释放后，金属线间距不再被极度压缩，因此 High-NA 机台可以通过单次曝光直接成型。而在没有背面供电的设计中，布线极其紧密，即使动用 High-NA 依然要被迫采用多重曝光，因此 High-NA 在经济上便毫无吸引力。正如英特尔工程师所指出的：“High-NA 正是一个绝佳案例，说明即便面对同一套设备工具，我们与台积电由于底层工艺架构的不同，得出了完全相反的结论（And High-NA is a good example of where, because of the architecture of our technology versus TSMC's, we make different conclusions off of the same tool set）。” - **光学参数对比**：标准 EUV 数值孔径为 0.33 NA；High-NA EUV 提升至 0.55 NA。 - **单次解析力**：High-NA 在单次曝光（Single pass）下打印的特征尺寸比标准 EUV 缩小 1.7 倍。 - **设备成本量级**：标准 EUV 约为 2 亿美元/台，High-NA EUV 约为其两倍（约 4 亿美元/台）。 --- ### `15:00` 从 IDM 到代工厂：PDK 的转型阵痛与历史基因 随着英特尔向外部客户开放代工服务，芯片设计公司需要根据英特尔提供的工艺设计套件（PDK，包含该节点制造规则与元器件库的菜单标准）来设计芯片。在 14A 节点上，High-NA EUV 是否启用被设为 PDK 中的可选项，由英特尔与客户逐案磋商决定。然而，在先前的 18A 节点推进过程中，外界曾传出英特尔 PDK 存在延迟、部分设计指令无法正常执行以及外部客户适配受阻等消息。 面对这些质疑，英特尔直面了向纯代工（Foundry）模式转型的陡峭学习曲线。在过去几十年的整合元件制造商（IDM）历史中，英特尔一直是“自研自产”，晶圆厂工艺团队直接和内部产品设计团队对接，直接分享晶体管的原始数据，彼此有极高的默契和私有规则，根本不需要交付正式的、标准化且极度严格的商业 PDK。正如英特尔受访者所坦言：“从如何转型成为代工厂的角度来看，这里面绝对存在一段学习曲线，而这也是我们的竞争对手曾经走过的道路（There's definitely a learning curve to how you become a foundry, and that's something that our competitors have gone through as well）。” 通过外部代工客户的直接反馈，英特尔逐步对齐了代工行业对 PDK 成熟度（例如 0.9 版与 1.0 正式版的技术交付标准）、质量规范及技术参数的严苛要求，并在 14A 的 PDK 中全面内置这些标准。在历史上，英特尔的晶圆厂只服务自己的芯片，而台积电由于长年服务外部多元客户，通过海量的晶圆出货积累了更密集的学习反馈、更多的再投资资金以及更准时的交付纪律。访谈在此处引申探讨了技术演化的偶发性：如果从 1960 年代开始科技树产生细微扰动，现代计算架构是否可能走向一种完全不使用铜互连、甚至没有全环绕栅极概念的平行世界；而像背面供电这种需要将整个硅衬底剥离打磨的极端构想，在 1990 年代看来完全是不可思议的异端邪说。 - **IDM 历史遗留问题**：过去英特尔内部设计与制造高度绑定，缺乏商业晶圆代工厂所需的标准化 PDK 机制与交付文化。 - **代工与 IDM 飞轮效应差异**：台积电依靠多元客户的庞大晶圆吞吐量，形成了良率优化与工艺迭代的滚雪球优势。 - **背面供电的工艺颠覆度**：在 90 年代，为了布线而把芯片底部的硅衬底完全剥离磨薄的方案，被视为极其脱离实际的想法。 ### `20:00` 突破铜导线极限与三维晶体管（CFET）的未来 在极微观的尺度下，芯片的物理结构正在发生颠覆性的改变。虽然铜导线在很长一段时间里都是无可争议的最佳选择，但在极度微缩的间距下，铜的物理极限正逼迫工程师寻找替代材料。随着全环绕栅极（GAA）晶体管和背面供电（Backside Power）技术的引入，芯片不再是简单地在基底上向上堆叠。晶体管现在仿佛“悬浮”在互连层之中。这种架构的改变激发了人们对真正三维堆叠的想象：既然存储芯片（如 3D NAND 和 DRAM）已经实现了惊人的三维结构，为什么逻辑芯片不能也走上这条路？尽管许多人认为由于散热等技术限制，未来五年内无法实现逻辑芯片的完全三维堆叠，但如果将时间跨度放大到 10 年、20 年，到 2045 年，各种奇异的三维结构将变得完全可行。 这种向上构建的思路首先体现在晶体管本身的堆叠上。目前的芯片由 N 型和 P 型两种晶体管配对组成，它们并排排列。而下一代技术——互补场效应晶体管（CFET）——则计划将它们直接上下堆叠。理论上，这能在相同的面积内塞进两倍的晶体管。然而，每增加一层都会带来成倍的制造步骤、成本以及致命的热量积聚问题。由于逻辑芯片的功耗远高于存储芯片，它无法像 HBM（高带宽内存）或 3D NAND 那样轻松进行 3D 堆叠。限制计算能力的核心因素有三个：器件的开关速度（频率）、开关所需的功耗（能效），以及如何散发开关产生的热量（散热）。目前，针对三维器件的系统级分析和模拟工具仍处于起步阶段，散热将是长期制约性能的瓶颈，但这些问题终将在工程投入中得到解决。 - **铜的替代必然性**：英特尔专家指出，“我认为对于一些最紧密的间距，用其他材料替代铜是不可避免的。” - **技术能见度限制**：行业对技术微缩的清晰能见度通常只有大约 4 年，超出这个时间跨度预测未来会变得非常困难。 - **CFET 的优势与挑战**：CFET 通过垂直堆叠 N 型和 P 型晶体管，理论上可将晶体管密度提升一倍，但面临极大的散热和制造复杂度挑战。 ```mermaid flowchart TD accTitle: 晶体管排列演进：从平面到三维堆叠（CFET） accDescr: 展示了晶体管从传统的并排排列演进到垂直堆叠的CFET结构，以节省空间。 subgraph Traditional ["传统并排排列"] N_Side["N型晶体管"] <-->|"占用双倍水平面积"| P_Side["P型晶体管"] end subgraph CFET_Stack ["CFET三维堆叠"] N_Top["N型晶体管 (上层)"] P_Bottom["P型晶体管 (下层)"] N_Top === P_Bottom end Traditional -->|"演进为"| CFET_Stack ``` --- ### `23:33` 英特尔“热门议题”会议与决策艺术 在英特尔，决定如何分配有限的工程时间和实验晶圆是一项极具挑战的任务。Dwarkesh 旁听了英特尔的“热门议题”（Hot Topics）会议，该会议由集成工程师凯文·费舍尔（Kevin Fisher）主持，旨在解决 18A 和 18AP 先进工艺节点的良率与性能瓶颈。在这个会议上，气氛紧张而高效，凯文扮演着“拍板者”的角色。他指出，普通工程师往往专注于技术细节，缺乏对商业大局的认知，而他的职责就是在不完整的数据面前权衡风险，决定是否开始冒险进行量产。为了加速实验，英特尔工厂采用了一种名为“热箱”（Hotbox）的层级系统。其中最高级别的“Hotbox 1”在工厂的每台设备上都享有绝对的优先通行权，就像高速公路上的共乘车道，虽然这会降低整座工厂的运行效率，但能让关键实验以最快速度完成。 会议讨论的一个具体技术难题是“外延结节”（Epi Nodules）。外延（Epitaxy）是指在现有晶体结构上像“长肿瘤”一样生长出异常的晶体结构，这会导致晶体管之间发生短路。为了解决这一问题，团队通常会并行开展多项研究，包括开发特殊的清洁工艺来消除已生成的结节，或者直接从源头上阻止结节的产生。 有趣的是，英特尔硬件的底层设计也为其他领域的创新提供了土壤。例如，英特尔芯片在过去十年中一直配备了一项名为“处理器跟踪”（Processor Trace）的功能，能够记录程序运行的每一个函数调用。量化交易巨头简街资本（Jane Street）的一位工程师注意到了这一功能，并与一名暑期实习生共同开发了名为“Magic Trace”的开源调试工具。这个完全自下而上的项目如今已被简街资本的交易员和开发人员每天使用，用于捕捉交易系统中转瞬即逝的网络延迟等微秒级异常。 - **不完整数据下的决策**：凯文·费舍尔强调了决策的紧迫性：“如果你想等待完整的数据集，那你等得太久了。那就已经太迟了。” - **工程师与商业现实的脱节**：凯文指出：“普通工程师通常不理解这其中的利害关系，也不明白这对应英特尔的底线以及我们的客户会产生多么紧迫的影响。” - **“热箱”（Hotbox）机制**：Hotbox 1 批次在工厂中拥有最高优先级，会打乱正常的生产排程，导致工具使用效率下降，但能以极限速度推进关键实验。 - **外延结节（Epi Nodules）**：在外延生长源极和漏极晶体时产生的异常晶体生长，会导致晶体管短路失效。 ```mermaid flowchart TD accTitle: 晶圆厂“热箱”（Hotbox）优先级流程 accDescr: 展示实验晶圆通过Hotbox 1快速通道与普通晶圆在生产线上的流转对比。 subgraph Highway ["晶圆厂生产线（类比高速公路）"] NormalLane["普通车道（普通晶圆批次）"] CarpoolLane["共乘车道 / Hotbox 1（实验晶圆批次）"] end Exp["高优先级实验晶圆"] --> CarpoolLane Prod["普通生产晶圆"] --> NormalLane CarpoolLane -->|"在所有设备享有绝对优先权"| FastTrack["超快速通关"] NormalLane -->|"避让Hotbox批次，设备利用率降低"| SlowTrack["常规流转"] FastTrack -->|"快速获取实验数据"| Decision["热门议题会议决策"] end ``` --- ### `29:30` 寻找铜的替代者：钌（Ruthenium）与互连层挑战 随后，Dwarkesh 随杰克·卡瓦列罗斯（Jack Cavalieros）参观了英特尔的研究实验室，探寻那些尚未进入量产阶段的前沿技术。他们首先关注的是芯片的“血管”——互连线（Interconnect）。在现代芯片中，晶体管上方堆叠了十几层由金属导线组成的互连网络。然而，随着导线尺寸的不断缩小，传统的铜导线开始遭遇严重的物理瓶颈，电阻急剧上升。为了解决这一难题，英特尔的研究人员正在积极探索使用钌（Ruthenium）等新型金属来替代铜，以确保未来芯片在极微观尺度下依然能够保持高效的信号传输。 - **互连层的重要性**：杰克·卡瓦列罗斯指出，晶体管只有在相互连接时才有用，现代芯片需要十几层金属线堆叠在晶体管上方。 - **铜的物理局限**：随着导线宽度缩减至纳米级，铜的电阻率急剧上升，限制了信号传输速度并增加了功耗。 - **钌（Ruthenium）的探索**：作为一种候选替代金属，钌在极细微的尺寸下表现出比铜更优异的导电特性和抗电迁移性能。 ### `30:00` 突破互连极限：钌（Ruthenium）与铜的物理博弈与量产抉择 在芯片内部微缩至纳米尺度时，金属互连线（Interconnects）的电阻问题变得极为棘手。虽然钌（Ruthenium）本身的体电阻率（bulk resistivity）高于铜，但英特尔仍在积极探索将其作为未来的互连材料。英特尔研发人员解释，传统铜导线在极小尺寸下会遭遇严峻瓶颈：为了让铜能够顺利沉积、牢固附着并与下层金属良好互连，必须预先在沟槽中涂覆一层“衬层”（Liner，类似过渡层或胶水层）。然而，钌与铜存在本质差异——钌是一种可以直接进行干法刻蚀（etch）的金属，因此完全不需要这层衬层。 当线宽持续缩减时，这层高阻抗的衬层在整条极细导电通路中所占的截面积比例就会越来越大。一旦摆脱了衬层的厚度开销，直接采用无衬层的钌走线，钌的有效导电性能反而会在极小尺寸下反超铜。英特尔指出，这种性能交汇点（crossover point）大约出现在 20 纳米节距（pitch）附近——这意味着大约 10 纳米是导电金属线，另外 10 纳米是用以绝缘的介电层。 谈及技术何时成熟到可以投入高通量制造（HVM），Dwarkesh Patel 提到了英特尔在 10nm 节点上从铜切换到钴（Cobalt）所经历的技术波折，询问如何断定一项技术在大规模制造中切实可行。研发人员坦言，将新材料整合进复杂的晶体管生态系统绝非单纯衡量可微缩性，还要看生态兼容度与集成难度。彼时选择钴，是因为在当时的实验数据中钴的表现更为领先；但随着全球供应商生态系统在机台工具与工艺上的持续改进，工程团队在后来的开发中重新找到了把铜做薄、使衬层进一步缩微的方案，让铜重新焕发竞争力。正如受访工程师所总结的： > “Every technology that we go through we will evaluate multiple options. And as we get closer to our time horizon for delivering a manufacturing-worthy product, we have to make a decision.” - **衬层的物理限制**：铜互连需要双重阻挡层与黏附层，在超窄线宽下，高电阻衬层占据了过多的截面积，导致铜线整体有效电阻激增。 - **钌的免衬层工艺**：钌具备直接刻蚀能力，从而省去衬层，在约 20 纳米节距及以下尺寸展现出比铜更优越的综合导电率。 - **制造抉择的动态演变**：早前钴在特定节点是领头羊，但随着设备商与材料商协同攻坚，铜的工艺被推向新极限，而面向未来极限尺寸，钌又成为了下一个极具潜力的候选者。 --- ### `32:41` CFET 晶体管垂直堆叠：从实验室简化原型到高深宽比制造挑战 CFET（互补场效应晶体管，Complementary FET）被业内视为晶体管垂直堆叠的终极演进方向。其核心理念是将以往水平并排摆放的 NMOS 和 PMOS 晶体管上下叠放，从而在物理平面上释放原本必须过度压缩的面积。英特尔正与行业竞争对手及全球外部实验室同步评估这一架构。然而，堆叠并不只是单纯“叠汉堡”，上下晶体管之间依然需要电学互连。受访工程师指出，过去在顶部或背面进行的走线，现在必须垂直穿插在两层晶体管之间，这带来了前所未有的超高深宽比（aspect ratio）挑战： > “The aspect ratio of creating trenches and filling those trenches becomes more and more difficult. So it's not as straightforward as stacking the transistors because you still have to think about interconnecting them.” 深宽比难题不仅体现在刻蚀必须打出深邃垂直的孔道，更体现在随后的材料填充环节——在纳米级的极狭窄缝隙中灌注金属与绝缘介质时，极易残存气隙（air gaps）或无法填满的空洞（voids），这对于先进制程是不可接受的缺陷。 为了研发这类复杂的全新架构，实验室不能每次都花费数月时间去走完包含上千道工序的完整制造循环。研发团队采用了一种称为“短环测试载体”（short-loop vehicles）的开发模式。研究人员会把晶体管工艺拆解为基础单元（unit cells），在实验室里单独测试二极管（diode）或电容器（capacitor）等底层元器件，快速获取电学与化学参数以排除技术障碍。在 CFET 的早期开发阶段，实验室并不会一上来就制造四层纳米带堆叠在四层纳米带之上的复杂结构，而是退回到“单纳米线对单纳米线”（one wire for NMOS on one wire for PMOS）的极简模型，以此在可控的工艺难度下验证叠层器件的物理特性与垂直互联表现。 ```mermaid flowchart TD accTitle: CFET 研发与验证进阶路径 accDescr: 展示从底层基础单元到短环验证载体，最终推进至全尺寸量产 CFET 的完整研发流程。 subgraph UnitLevel ["1. 单元级测试 (Unit Cells)"] D1["基础元件制备<br/>(二极管 / 电容)"] D2["快速反馈与参数标定<br/>(电学/化学特性验证)"] D1 --> D2 end subgraph ShortLoop ["2. 简化版原型 (Short-Loop Vehicles)"] S1["单层 NMOS 纳米线"] S2["垂直互联与中介层"] S3["单层 PMOS 纳米线"] S1 --- S2 --- S3 end subgraph ProductionScale ["3. 终极量产构型 (HVM CFET)"] H1["多层纳米带上下垂直堆叠<br/>(如 4 Ribbon on 4 Ribbon)"] H2["高深宽比深孔刻蚀与无气隙填充"] H3["与背面供电系统完全集成"] H1 --> H2 --> H3 end D2 --> ShortLoop ShortLoop --> ProductionScale ``` --- ### `35:45` 为什么前沿技术需要十年落地？二维材料与研发中的“死胡同” Dwarkesh Patel 提出疑问：既然实验室里已经掌握了极小特征尺寸（如利用 EUV 或电子束光刻 e-beam），甚至已经制造出能在实验室中工作的 CFET 原型，为什么这项技术从实验室走向普通人的智能手机仍旧需要长达十年之久？ 英特尔工程师解释，这涉及全新材料与全新架构之间的本质区别。对于像过渡金属二硫属化物（TMDs，Transition Metal Dichalcogenides）这类超薄单原子层二维材料（2D materials），实验室虽然已经具备原子级精度的沉积技术，并能通过光刻制造出极微小的接触点以调控其导电性，但把它们从实验室小样推向量产，背后是庞大复杂的工程长尾问题。研发人员直言： > “There's a thousand different steps that all have to come together in a very unique way to make the performance compatible or actually supersede the prior technology.” 实验室制造出来的极简 CFET 原型，其单片器件综合性能根本无法超越现有的成熟水平并列式纳米带（RibbonFET）技术。要想实现技术迭代的代差优势，团队必须从单根纳米线演化为双纳米带甚至多纳米带，并精巧调配多层金属栅极与特定介电常数的介电质，以榨取全部性能潜力。 在筛选数十种前沿构想（如新型二维材料）的过程中，大量方案会在真实集成环境中撞上物理或化学“死胡同”： 1. **界面附着失效（Adhesion Failure）**：第一阶段的沉积实验看似很完美，薄膜均匀平整且可以精确测量；但在进行下一步工艺尝试为其制作电极接触时，金属或中介层根本无法附着在该材料表面，工艺直接中断。 2. **后道气相反应与化学不兼容**：即便成功沉积并对材料进行了覆盖层（capping layer）包裹，如果这层覆盖并不具备完全的气密性（hermetic），在随后的第三、第四道后续高温或气相工艺中，工艺气体仍会渗入并改变二维材料的基底性质，导致晶体管特性极度不稳定。如果找不到切实可行的气密密封解决方案，该材料方向就会被彻底废弃。 在微观层面，堆叠晶体管（CFET）目前依然留在前沿探索的实验室阶段；而在宏观系统层面，另一种“堆叠”——将不同功能的完整芯粒在三维空间中堆叠封装（Chip Stacking / Packaging）——已经全面进入量产，开启了彻底改变芯片间通信瓶颈的新战场。 ### `40:00` 封装技术的演进与“面积 vs 周长”瓶颈 在现代 AI 计算中，芯片互连已成为决定性能的核心瓶颈。以英伟达（NVIDIA）的 Blackwell 数据中心 GPU 为例，它将两颗巨大的计算芯片连接在一起，外围环绕着 8 堆高带宽内存（HBM）。这些芯片之间必须以极高的频率进行数据传输。在 AI 负载中，往往不是芯片本身的绝对计算能力，而是芯片间的数据传输速度决定了任务最终的完成效率。随着晶体管密度越来越高，芯片计算能力的增长速度远快于其向外搬运数据的速度，这就是半导体行业熟知的“面积与周长问题”（Area versus perimeter problem）。 ```mermaid flowchart TD accTitle: 芯片封装互联架构演进 accDescr: 展示芯片封装从平面并排连接、2.5D中介层连接，到使用焊锡凸块的直接键合，最终走向无焊锡铜对铜混合键合的演进流程。 subgraph SG1["传统与 2.5D 方案"] A["传统平面封装<br/>（Side-by-Side 走线，间距宽、延迟高）"] B["2.5D 封装<br/>（引入硅中介层 Interposer 走线）"] A --> B end subgraph SG2["直接键合技术演进"] C["传统 3D 键合<br/>（采用焊球 Solder Bumps，体积大、电阻高）"] D["混合键合 Hybrid Bonding<br/>（无焊锡铜对铜热熔合 + 介质键合）"] B --> C C --> D end ``` 为了应对这一挑战，芯片制造完成后必须经过的两道关键工序——键合（Bonding）与封装（Packaging）——在过去几十年中发生了根本性转变： - 最初，芯片只是并排摆放（Side-by-side），连接导线直接从芯片侧边引出连接到另一颗芯片。 - 随后，业界引入了一块共享的硅片，即硅中介层（Interposer），让多颗芯片立于其上，导线直接穿过中介层相连，这种技术通常被称为 2.5D 封装。 - 为了进一步提升互连密度，芯片开始直接垂直叠放在一起，但早期方案依赖微凸块（Solder bumps/焊球）。焊球体积相对庞大且会增加电阻。 - 最前沿的技术则是跳过焊锡，直接将两颗芯片的信号导线熔合在一起，即“混合键合”（Hybrid Bonding）。该技术通过对齐两颗芯片的铜互连线，施加压力并加热，使铜膨胀并消除间隙相接，同时四周的绝缘介质表面也结合在一起。这种技术去除了焊球，从而大幅提高了互连密度。 --- ### `43:00` 晶圆对晶圆 vs 芯片对晶圆：混合键合的良率与架构抉择 在探讨混合键合的具体实现时，行业内主要有两种路线：晶圆对晶圆（Wafer-to-Wafer）与芯片对晶圆（Die-to-Wafer / Chip-to-Wafer）。英特尔先进封装技术开发团队的总监解释了两者的技术差异与工程权衡。 “晶圆对晶圆”是将整块未切割的晶圆与另一块晶圆直接压合在一起。这种方法目前在 CMOS 图像传感器（CIS）领域被普遍采用甚至处于主导地位，也有人尝试将其用于内存堆叠。然而，它的核心缺陷在于严苛的物理与良率限制： 1. **尺寸对称限制**：两颗芯片必须在尺寸上保持一比一匹配，上下设计必须能够绝对对准，如果上下两层芯片面积不一致就无法实施。 2. **良率随机乘数损失**：两块晶圆在测试分选（Sort）时，各自的良品芯片（Good Die）与不良芯片（Bad Die）在空间分布上通常是随机的。如果两张晶圆的良品位置无法完全重合，就会发生“良品芯片与次品芯片强行键合”的情况，导致良品损失。 相比之下，“芯片对晶圆”路线允许厂商先对晶圆进行物理切割（Singulate），在芯片级别完成测试，确认是“已知合格芯片”（Known Good Die, KGD），然后仅将已知合格芯片贴合到底层晶圆的对应合格位置上。英特尔总监指出：“客户与芯片架构决定了采用哪种方式，但在逻辑芯片对逻辑芯片（Logic to Logic）的领域，芯片对晶圆显然极具吸引力。”不过，英特尔在技术能力上对这两种方案都保持着支持。 --- ### `45:00` 间距微缩至亚微米：混合键合带来的能效与互连革命 封装技术的演进历程本质上是互连间距（Pitch）不断微缩的历史。英特尔总监回顾并展望了间距尺度的演变： - **15 年前**：第一代芯片级互连的间距约为 130 到 150 微米。 - **当前量产（HVM）**：英特尔的 Foveros 3D 封装技术正在实现 25 微米间距。 - **目前混合键合研发**：间距已经缩小到 10 微米以下（Sub-10 micron）。 - **行业最前沿研究**：在当年 5 月举行的电气与电子工程师协会电子元件与技术会议（IEEE ECTC）上，已经有学术论文公布了间距仅为 0.45 微米的混合键合器件可靠性数据。 这一数据意味着封装互连密度将再次跨越一个数量级。晶圆制造后道（BEOL，即封装层下方的金属走线）的尺度通常在 0.5 微米到 1 微米左右。如果先进封装的间距能推至 0.5 微米或更小，芯片设计理念将迎来剧变： - 工程师可以直接从芯片顶层剥除多余的互连层，实现一层硅片中较低层级的金属走线与另一层硅片中较低层级的走线直接互连。 - 减少双侧芯片的互连层数后，两层晶体管之间的总电压降（IR drop）将显著降低。 针对非 AI 类应用（如客户端 PC 芯片），混合键合同样具有决定性优势。除了能为 CPU 与 GPU 之间提供极致的物理带宽密度，更核心的优势在于能效：随着互连间距不断微缩，接口的数据传输能耗（以皮焦耳/比特，pJ/bit 计算）大幅下降。英特尔总监强调，混合键合能直接压低整个系统的功耗预算，在保持相同电气性能的前提下，实现更低的功耗与发热。 --- ### `48:00` 设备产能天花板与 18A 到 14A 的工具复用难题 制造更好芯片的技术路线已经明晰，但另一个核心难题是：即便 AI 实验室愿意掏出海量资金，半导体工业界的物理工具产能是否跟得上？Dwarkesh Patel 就供应链瓶颈问题对话了英特尔首席技术官（CTO）Pushkar Ranade。 Dwarkesh 指出，荷兰阿斯麦（ASML）每年的极紫外光刻机（EUV）年产量还不足 100 台，且到 2020 年代末之前也没有大幅突破 100 台的扩产计划；而这有限的产能还必须由英特尔、台积电（TSMC）以及 SK 海力士等所有内存大厂共同瓜分。对于这一严峻制约，Pushkar Ranade 回应道： > “这确实是一个限制因素。因此，我们必须最大限度地利用已经安装好的产能，并努力提高现有设备机群的产出率。” > (“It is a limiter. So we have to make the most of the capacity that we already have installed, and we'll try to increase the output from our existing fleet of tools.”) Pushkar Ranade 进一步揭示，ASML 的 EUV 并非唯一的瓶颈，几乎所有类型的半导体制造设备都在面临巨大的供应短缺。半导体生产的残酷之处在于工艺锁定： - 一旦某套工艺流程（例如英特尔的 Intel 18A）研发成熟并定型，它就与特定厂商的特定机台型号深度绑定。 - 制造厂无法随意采购其他供应商的同类设备来替代，这导致芯片代工厂在设备交付周期上完全受制于单一供应商。 面对 2028 年即将到来的 Intel 14A 节点，英特尔的应对策略是追求跨代机台的“通用复用性”（Fungibility）。行业通常的做法是，在从一个制程节点演进到下一个节点时（如从 18A 跨入 14A），力保约 80% 的设备机群可以被直接沿用，仅针对需要更高晶体管密度的新特性引入专用的新型机台设备，从而在供应链极端短缺的环境下维持扩产弹性。 ### `50:00` 芯片产能的全球物理瓶颈与“伪垂直整合”浪潮 当 Dwarkesh Patel 询问即使投入无限资本开支（CapEx），英特尔乃至全球晶圆厂每月能生产的晶圆极限究竟受限于什么时，英特尔首席技术官指出，在现有的工具基准下，提升产出只能是渐进式的，因为当前先进制程的良率已经处于极高水平，要在高度微调的工艺上每挤出 1% 的良率提升都异常艰难。Dwarkesh 追问，全球现有的半导体制造设备产能是否足以支撑先进制程晶圆产出实现 10 倍的扩张。对此，首席技术官给出了一个令人清醒的判断：“不是 10 倍，但大概能翻到 2 倍，是的（Not 10x, but probably like 2x, yes）。”这与过去十年人工智能行业算力需求每年增长 3 倍的现实形成了剧烈反差。英特尔首席技术官直言，这种算力扩张的供应链瓶颈是全局性的： > “除非整个供应链——从设备供应商、他们的供应商再到下游的子供应商——所有人都能提高产量，否则大家无法共同增加产出。” 随后，两人探讨了整个技术栈中价值分配的奇特现象。Dwarkesh 计算指出，英特尔只需投入几十亿美元的资本开支，其生产的逻辑芯片就能为上层的 AI 大模型公司撬动每年高达 1000 亿美元的营收；这种资本支出的高杠杆回报，按理说应该倒灌至硬件制造端，甚至促使 AI 实验室为锁定未来晶圆产能直接开出空头支票、包圆整座晶圆厂。英特尔首席技术官确认已经出现了这种早期信号。他分析道，半导体产业在三四十年前是完全垂直整合的，随后演化为横向分工模式（晶圆代工厂、设备商、无晶圆厂设计公司各司其职）；而今天，由于头部超大规模云厂商（Hyperscalers）的体量过于庞大，且都在自主设计芯片，个别厂商的需求足以吞吐一整座乃至多座晶圆厂的全部产能。行业正在从横向分工重新走向一种“伪垂直整合”或虚拟垂直整合的时代。 ```mermaid flowchart TD accTitle: 半导体产业架构演进 accDescr: 展示半导体产业从早期垂直整合，到水平专业分工，再到由超大规模云厂商主导的虚拟垂直整合的演变历程。 subgraph S1["早期架构 (30-40年前)"] A["垂直整合制造 (IDM)<br/>设计与制造一体化"] end subgraph S2["传统现代架构 (水平分工)"] B1["设备/材料供应商"] --> B2["专业代工厂 (Foundry)"] B2 --> B3["无晶圆厂芯片设计 (Fabless)"] end subgraph S3["当前新兴架构 (虚拟垂直整合)"] C1["超大规模云厂商 (Hyperscaler)"] -->|"包揽全厂产能 / 自研芯片"| C2["先进制程晶圆厂"] end ``` - 全球设备供应极限：即便资本无限，全球供应链的物理产能目前也仅能支撑先进制程晶圆产出翻倍（约 2 倍），根本无法支撑 10 倍的产能跃升。 - 价值分配倒挂：底层数十亿美元的逻辑芯片制造 CapEx 在上层大模型软件端可催生每年约 1000 亿美元营收。 - 产业形态转变：超大规模云厂商凭借充沛资本与自研芯片需求，开始以类似长期锁定整座工厂产能的方式，重塑半导体产业的组织形态。 --- ### `53:14` 晶圆制造的规模经济与仅存的三巨头格局 谈及台积电在先进制程出货量上超过英特尔 3 倍的规模优势，Dwarkesh 询问晶圆制造中的规模经济是否存在边际递减效应。英特尔首席技术官表示，先进制程代工可能是全工业界中规模经济体现得“最纯粹”的领域。其核心原因在于天文数字般的固定成本沉没： > “其原因在于固定成本高得难以置信，一旦建好一座晶圆厂，你的成本结构中大约 80% 都是固定的。” 在高达 80% 固定成本的约束下，晶圆厂产能利用率每提高 1 个百分点，带来的都是纯利润与收入的剧增。与此同时，良率的提升同样呈现出极其显著的非线性回报：如果工艺改进将芯片良率从 60% 提高到 65% 或 70%，在工厂物理占地面积（Footprint）完全不变的情况下，净产出将出现爆发式增长。这正是半导体制造历史上残酷整合的根本驱动力。四十年前全球尚有 20 多家能够制造先进制程的晶圆厂，而随着建厂成本呈指数级攀升，无法维持巨大吞吐量和高利用率的厂商被逐一淘汰，最终全球先进制程赛道仅剩台积电、英特尔和三星三家巨头。 - 成本结构：晶圆制造厂约 80% 的成本为固定资产折旧等固定成本，运营必须追求极高的设备利用率。 - 良率非线性：固定厂房空间内，微小的良率提升（如 60% 升至 70%）能带来不成比例的巨额商业回报。 - 行业洗牌：极端的规模经济壁垒导致过去四十年间全球先进制程制造商从 20 余家骤减至如今的 3 家。 --- ### `55:00` 追赶台积电的现实路径：规模、执行力与制程之争 面对台积电先进制程（如 N3）已被英伟达等 AI 加速器以及算力集群伴生的大量高性能 CPU 挤爆的现状，Dwarkesh 询问英特尔追赶台积电的具体方案。英特尔首席技术官明确区分了“规模差距”与“技术差距”。他承认，台积电目前的晶圆出货规模远超英特尔和三星，要在生产规模上追平将是一个漫长而渐进的过程。但就底层制造技术本身而言，他给出了极其自信的评价： > “如果是指纯粹在技术上赶超，我认为我们已经做到了。” 他阐述道，业内热衷于对代工厂进行单一维度的跑分对比，但如果两家厂商的技术处于同一代级，性能、功耗或面积密度（PPA）上百分之几的微小差异在商业层面上其实无足轻重。只有在拉开整整一到两代的技术断代时，性能与功耗的优劣才会对芯片面积与产出造成实质性打击。在技术水平相近的区间内，“准时交付（Execution）和提升良率以支持大规模、高速度的产能爬坡，远比在性能或面积上硬抠百分之几的差距要重要得多。” 针对半导体行业分析机构（如 SemiAnalysis）关于“英特尔 2028 年推出的 14A 制程晶圆密度可能仅与台积电 N2 相当”的推测，英特尔首席技术官直接反驳了该对标基准的合理性。他指出，现代制程不是单一维度的晶体管密度比赛，任何一个先进制程节点（如 18A 或 14A）都必须提供包含低漏电晶体管、高驱动电流晶体管、高密度 SRAM、高性能 SRAM 以及模拟电路与射频（RF）电路在内的完整器件库，技术竞争力是所有这些复杂维度的综合体现。 在资本开支方面，台积电当年 CapEx 预计达到 500 亿美元左右，而英特尔约为 200 亿美元。首席技术官解释道，台积电当前是面向全行业的代工厂，而英特尔现阶段主要仍是满足自身产品线，未来随着英特尔代工业务（IFS）面向外部客户全面铺开，其 CapEx 规模也会相应扩张。在对话尾声，Dwarkesh 提及英特尔最初在 1960 年代末以 DRAM 存储起家，但后来退出了 DRAM 并在近年剥离了 NAND 闪存业务（Solidigm），而在如今 AI 浪潮推动下，存储器已演变为数万亿美元的暴利赛道。对此，首席技术官坦率地自嘲道：“显然，事后看来，卖掉闪存业务可能并不是最明智的时机。”不过他也补充，在做出剥离决策的当时确实存在合理的战略考量，彼时全行业无人能预料到如今由 AI 引爆的极端算力与存储饥渴。 - 追赶维度分化：英特尔认为自己在制程技术本身已基本追平台积电，真正的差距在于代工规模与产能爬坡的执行力。 - 制程评价的多维性：先进制程竞争力绝非单纯对比晶体管密度，而是涵盖低漏电、高驱动电流、高密度 SRAM、RF 等器件生态的综合工程。 - 存储业务剥离反思：英特尔早年剥离 DRAM、近年出售 NAND 闪存业务，在事后看来错过了当前 AI 对高带宽与海量存储需求的爆发红利。 ### `01:00:00` 算力瓶颈与2030年产能死局 对话伊始，两人谈到了当前 AI 算力与内存供应的极度紧缺。对方直言，市场会吞下所有能造出来的算力芯片，也会吃光所有能造出来的内存芯片；甚至可以断言，当下的供应链危机中，内存端面临的短缺比算力端还要严重。 ```mermaid flowchart TD accTitle: 芯片扩产时间线阻碍 accDescr: 展示从采购设备到晶圆厂投产的时延导致2030年前产能上限被锁死 subgraph Timeline["扩产时间线"] A["2026年中期: 下达海量设备订单"] B["18个月交期: 延宕至2028年"] C["新建外壳与无尘室 (Fab Shell)"] D["2030年末: 新增有效产能释放"] end A --> B B --> C C --> D ``` Dwarkesh Patel 试图梳理对方对产能预测的核心逻辑：短期内边际产能确实可以在大约12个月内快速提升，但在本十年末（2030年前）的整体产能上限却极难突破。即使明年的产出可能高于预期，2030年的总产能也绝不会显著超出当前预估。对此，受访者深表赞同，并点明了供应链在物理规律面前的冷酷现实：“I mean, we're already in the middle of 26. So there's, you know, only not that many years until the end of the decade.” 现在的设备交付周期极为漫长，假设今天开出一笔天价光刻设备订单，单是等待交货就需要18个月，时间瞬间就来到了2028年；如果还要从零开始平地起高楼、建造晶圆厂的外壳（Fab Shell），等到全面投产，基本上就已经到了2030年代初。 - **边际短期爬坡**：现有产线优化可在12个月尺度见效。 - **长周期锁定**：从设备订单（约18个月交期）到新晶圆厂建筑完工，整个周期直接锁死2030年前的先进产能天花板。 - **上游结构性短缺**：受制于关键工具制造厂商的产能上限，除非整条设备供应链发生颠覆式扩产，否则全球顶尖芯片的总盘子无法迅速扩张。 ### `01:01:02` Terafab 与狂飙的建厂经济学成本 谈及马斯克（Elon Musk）对外宣称的“Terafab”愿景，Dwarkesh 询问英特尔与他的合作内幕。受访者解释，马斯克敏锐地察觉到其旗下所有业务对算力与内存硅片的爆炸性需求，并得出了“要么我们建造 Terafab，要么我们就拿不到足够的芯片”这一结论，甚至一度打算全部自主完成。然而制造芯片远非造车可比，其工艺精细度与试错代价不可同日而语，英特尔因此与他联手以期加速晶圆厂的建设。但 Dwarkesh 指出，如果真正的瓶颈卡在设备制造端，自建晶圆厂并不能增加全球硅片的净产出，充其量只是在跟其他晶圆代工厂争夺配额时获得某种内部“保底供应”。受访者承认芯片厂不仅需要海量机台，还需要极度庞大的电力、水源和耗材，更需要大量的洁净室空间。 晶圆厂急剧飙升的建厂成本已经逼近不可持续的临界点。受访者回顾道，过去三四十年间，建造一座先进晶圆厂的成本几乎每隔四到五年就翻一倍；在晶圆厂内部，最昂贵的光刻工艺模块成本翻倍速度甚至更为迅猛。如今单台 High-NA EUV 光刻机及配套设备的标价就已经高达4亿美元左右。按照这种指数规律外推，再过四年仅光刻成本难道要飙到8亿美元吗？这种近乎荒谬的重资本消耗，正倒逼行业去反思是否在某些根本性路线上走入了盲从的死胡同。 - **Terafab 动机**：马斯克预测到自身业务遭遇硅片断供风险，试图绕开传统代工厂争夺产能，但依然面临机台工具上限。 - **晶圆厂成本倍增律**：晶圆厂综合建设成本每4至5年翻一番，光刻模块成本增速更甚。 - **单机4亿美元天价**：High-NA EUV 及其配套设施的单价已经高达4亿美元，导致资本门槛变得极度畸形。 ### `01:03:30` 风险厌恶下的范式僵局：为什么没人敢在实验室抽雪茄？ 这种每座工厂动辄数百亿美元的投资体量，直接塑造了整个半导体行业极度规避风险（risk-averse）的行事作风。几十年来，所有工程师都被灌输了一套代代相传的标准流程并奉为圭臬：“And they just take that as gospel, right? That's just how it is done. But is that really the best way to build a chip today? It's a really valid question.” 受访者直言，这种极度保守不仅存在于制造端，也同样束缚着芯片架构设计——许多现代 CPU 的设计范式实际上是30年前就固化下来的产物。当 Dwarkesh 追问未来是会在光刻步骤上进行偷工减料，还是会彻底颠覆晶体管本身时，受访者表示从平面晶体管（Planar）到 FinFET，再到如今的全环绕栅极（Gate-All-Around），晶体管的技术路线图虽然清晰明确，但在基础设施层面却存在着不敢触碰的盲区：比如，现代芯片制造真的在每一个环节都需要如此精密苛刻的无尘室吗？ > “Surely one can run an experiment where people are eating hamburgers and smoking cigars in the research lab and see what happens to yield.” 面对 Dwarkesh 这个戏谑而充满挑战意味的假设——在研发实验室里一边啃汉堡、抽雪茄一边做实验来看看良率究竟会跌成什么样——受访者大笑并表示这确实是个绝妙的实验点子，但无论是英特尔、台积电还是三星，没有任何一家现有巨头敢主动承担这种风险。因为在先进工厂中，损失一天的停机产能就相当于蒸发掉难以估量的巨额财富。虽然摆脱对极端洁净室的依赖未来能省下不可思议的资金，但对未知的恐惧让大厂只能按部就班。他强调，正因如此，有时从零开始（clean slate）、彻底打破既有教条的反思才是必要的。 ### `01:06:54` 终局抉择：英特尔是否该像英伟达一样豪赌未来工具？ 访谈在尾声处回到了最开始的核心命题：面对汹涌而至的 AI 需求，英特尔究竟该如何应对？Dwarkesh 提出一个尖锐的建议：如果最底层的死结在于上游工具机台的短缺，而英特尔本身又手握现成的晶圆厂地皮并具备扩建能力，那么英特尔当下唯一明智的战略举措，就应该是凭借全部融资能力筹集最大规模的资本，像英伟达豪掷数百亿美元提前锁定上游内存与核心零部件供应链那样，把全世界未来几年的先进光刻工具全部买断包圆。否则，几年后当市场对芯片的渴求达到数万亿美元规模时，英特尔只会陷入看着台湾地区拥有所有机台而自己只能望洋兴叹的被动境地。 面对 Dwarkesh 的逼问，受访者坦承这是一个直击要害的深刻问题：“Had we known what we know today, we would have bought invested more like a year ago. Knowing what we know now, I think we'll be investing more.” 他公开承认，如果早在一年前就洞悉今日 AI 需求的狂暴程度，英特尔早就会下注更大规模的机台资本开支；而在当下看清了供需错配的宏观现实后，英特尔接下来的唯一选择必然是加大在核心制造设备上的投资力度，以防在未来的全球算力版图重构中失掉先机。 ## Notable quotes > `50:00` 除非整个供应链——从设备供应商、他们的供应商再到下游的子供应商——所有人都能提高产量，否则大家无法共同增加产出。 — 英特尔首席技术官（Pushkar Ranade） > `03:22` 你不能在一个制程节点里塞进太多的技术创新。因为你引入的创新越多，系统就会变得越复杂。 — Chris Auth > `23:33` 如果你想等待完整的数据集，那你等得太久了。那就已经太迟了。 — Kevin Fisher > `53:14` 一旦建好一座晶圆厂，你的成本结构中大约 80% 都是固定的。 — 英特尔首席技术官（Pushkar Ranade） > `20:00` 我认为对于一些最紧密的间距，用其他材料替代铜是不可避免的。 — 英特尔专家 ## Mentioned Dwarkesh Patel, Chris Auth, Kevin Fisher, Jack Cavalieros, Pushkar Ranade, Elon Musk, Intel, TSMC, ASML, Samsung, NVIDIA, SK Hynix, Jane Street, WorkOS, Antithesis, Solidigm, SemiAnalysis, IEEE ECTC, Intel 14A, Intel 18A, Intel 18AP, Magic Trace, High-NA EUV, RibbonFET, PowerVia, Foveros, Blackwell GPU, Terafab ## Video description <p>Demand for AI compute has grown 3x a year for the last decade, but according to Intel’s CTO, there are only enough chipmaking tools in the world to roughly double leading-edge production.</p><p>I wanted to understand what innovations are coming out of the fabs, and what they mean for the future of computers, so I spent two days at Intel talking to the people working on them – from the head of process development to the research lab, the packaging group, and the CTO.</p><p>A lot of what’s coming next – gate-all-around transistors, backside power, CFET, hybrid bonding – is hard to follow without seeing it, so some of this video is the animated explainer I wish I had while I was prepping.</p><p>We haven’t done this format before, so let me know what you think!</p><p>I also made flashcards for the concepts I had to learn to prep for this episode <a target="_blank" href="https://flashcards.dwarkesh.com/">here</a>.</p><p>Watch on <a target="_blank" href="https://youtu.be/frYSOKvNiiE">YouTube</a>, read the <a target="_blank" href="https://www.dwarkesh.com/p/intel-tour">transcript</a>.</p><p>Sponsors</p><p><a target="_blank" href="https://workos.com">WorkOS</a> helps you do business with enterprises. It gives you access to all the features most commonly required by enterprises: SSO, SCIM, RBAC, audit logs, and more. It’s easy to plug these features in — it only takes a few lines of code — and WorkOS is releasing new functionality all the time, including things like auth for agents. If you want to join the 3,000+ companies that rely on WorkOS, go to<a target="_blank" href="https://workos.com"> </a><a target="_blank" href="http://workos.com">workos.com</a></p><p><a target="_blank" href="https://janestreet.com/dwarkesh">Jane Street</a> built a powerful tool called magic-trace to help analyze and debug their trading systems. It only exists because one engineer noticed a feature on Intel chips called Processor Trace and thought it’d be valuable to build on top of. Now, traders and developers across Jane Street use magic-trace every single day! If you want to be trusted to pursue the ideas you think matter most, Jane Street is hiring. Go to<a target="_blank" href="https://janestreet.com/dwarkesh"> janestreet.com/dwarkesh</a></p><p><a target="_blank" href="https://antithesis.com/dwarkesh">Antithesis</a>’ testing platform lets you perfectly reproduce every single bug you find. That’s because it runs on a fully deterministic computer, which strips out all the unpredictability that can make certain bugs flaky and hard to pin down. To build it, Antithesis found every source of non-determinism in Intel’s x86 architecture and either sealed it off or replaced it with a controlled simulation. Learn more at<a target="_blank" href="https://antithesis.com/dwarkesh"> antithesis.com/dwarkesh</a></p><p>Timestamps</p><p>(00:00:00) – Intro</p><p>(00:00:47) – How Intel brings up a new process node</p><p>(00:03:22) – What Intel learned from 10nm</p><p>(00:06:28) – From planar transistors to gate-all-around</p><p>(00:13:13) – Why High-NA EUV pays off for Intel but not TSMC</p><p>(00:19:20) – Could chips have evolved completely differently?</p><p>(00:23:33) – Inside Intel’s “Hot Topics” meeting</p><p>(00:29:30) – Replacing copper wires with ruthenium</p><p>(00:32:41) – Why stacked transistors take a decade to ship</p><p>(00:39:45) – Hybrid bonding and the chip-to-chip bottleneck</p><p>(00:48:00) – There aren’t enough tools to 10x chip production</p><p>(00:53:14) – Can Intel catch up to TSMC?</p><p>(01:01:02) – Terafab, and rethinking the fab from scratch</p> <br/><br/>This is a public episode. If you would like to discuss this with other subscribers or get access to bonus episodes, visit <a href="https://www.dwarkesh.com?utm_medium=podcast&#38;utm_campaign=CTA_1">www.dwarkesh.com</a> [Source](https://api.substack.com/feed/podcast/221632772/30c38515d3ea0554c60350beead67f42.mp3)

[50:00] 英特尔首席技术官（Pushkar Ranade）: 除非整个供应链——从设备供应商、他们的供应商再到下游的子供应商——所有人都能提高产量，否则大家无法共同增加产出。 [3:22] Chris Auth: 你不能在一个制程节点里塞进太多的技术创新。因为你引入的创新越多，系统就会变得越复杂。 [23:33] Kevin Fisher: 如果你想等待完整的数据集，那你等得太久了。那就已经太迟了。 [53:14] 英特尔首席技术官（Pushkar Ranade）: 一旦建好一座晶圆厂，你的成本结构中大约 80% 都是固定的。 [20:00] 英特尔专家: 我认为对于一些最紧密的间距，用其他材料替代铜是不可避免的。

[0:00] There's never been as big a shock to the semiconductor industry as the current surge in demand from AI. AI is driving incredible computing demand. Easily 40 to 50 percent above our maximum capacity, which I've never seen before. Progress in AI has been driven by exponentially increasing compute. To sustain that progress, foundries like Intel will need to manufacture far more leading-edge compute, both by producing more chips and by improving what each chip can do. from their suppliers, most famously, ASML's EUV machines. - If they don't have the equipment, they can't make the chips here. - I spent two days touring Intel's fabs to prepare for these interviews with its leadership. I wanted to understand what it takes to manufacture the world's most advanced chips, and how hardware is shaping the future of AI. Okay, I'm joined by Chris Auth, who leads development of all the processes that are currently under manufacturing. The thing I want to understand in more concrete detail is how the development of a new process actually happens. So if 14A is going to come out in three years or two years from now, what is happening from now till then? And I want you to walk me through as much detail as you can, everything from like the level of how is the yield improving? What kind of telemetry do you guys look at? What is what kind of experiments do you guys run? I want to understand what is going to happen over the next two years as concretely as possible. 14A. 14A has actually been in development for about three plus years at this stage. And so quite a bit of free work has been done to get to the stage that it's at right now. And right now we're getting very close to where we're finalizing the process. We're finalizing the tool sets that it will be manufactured on. And we're working on kind of the fine tuning of each of the process steps. There's about 2,000 steps in the factory that you have to go do and you need to do Really intricate work at each one of those to make sure it's fine-tuned. It can go into manufacturing. It can run thousands of wafers a week on this process, and it can be repeatable every single time. Right now, you might have a certain yield. Walk me through how that increases month over month. So there's a line running at 14A. What happens from now until next month that will result in the yield changing? How do you identify where the defects are? How do you fix that? Yeah, so there's a constant process that we go through in identifying defects. We'll identify defects. One is we have inline metrology. So we have tools that will look at the wafers and say, oh, there's a defect there. There's a defect there. There's a defect there. And then also at end of line, either electrical test or we sort and see where the fails are. And we will identify failures. And then we will get analysis on those failures. We'll cross-section it. You were in the TEM lab yesterday. And you saw how you can get cross-sections. You'll get a cross-section of a defect. And from that, you'll be able to say, oh, that defect is between these layers. to come from this section of the flow. Oh, we have inline metrology in that section, which has identified defects. Those are the defects we need to go after. I think what we've learned is that you don't want to do too much innovation in one node. Because the more innovation that you did, the more complex it becomes. And while that You'll be able to get that to work. You need to hit a certain schedule, and that's the schedule that your customer ultimately wants. So having that predictable schedule is a key piece. So you've got to figure out how much innovation you can put in in order to meet the requirements. customers' requirements in the timeline that they needed. Intel learned how costly that trade-off can be with delays to its 10-nanometer node, whose original target launch date was 2016, but which didn't begin manufacturing until 2018. You know, usually Intel has been the keeper of Moore's law, a new cadence of manufacturing every two years, but their last set of products slipped almost four years. Intel today having its worst day in four months, the stock now down more than 15%. semiconductor up 13% off of Intel's bad news. Walk me through what lessons you think Intel has learned from 10 nanometer. 10 nanometer was a good example of where we had very aggressive targets. We were doing what was called hyperscaling at the time. So we were scaling much faster than what had been historically done. In order to do that, we came up with all sorts of new tools because the tools weren't ready. And so that put a lot of burden on the process and a lot of burden on the engineers in order to do that. Now, at the end of the day, 10-8 is a great technology. It has world-class yield. It has world-class performance. It has world-class cost. But it took us longer to do that than what we would have liked. And so we've kind of tried to take that learning into future technology nodes and say, hey, we need to limit the amount of innovation we put in there to make sure that we keep it on schedule. What do you think was the main challenge? technology that was that should have been safe for a future version. EUV was was probably the big thing when we started to define 10 nanometer. the conclusion was, Yuvi was not ready. Yuvi [5:00] is extreme ultraviolet lithography. It prints chip patterns with light at a wavelength of 13.5 nanometers, about 14 times shorter than that emitted by previous tools that chip makers had relied on. The shorter the wavelength, the finer the features that a single exposure can print. But Intel decided this technology wasn't going to be ready in time. TSMC transitioned to EUV much sooner. It put EUV into volume manufacturing in 2019 and ramped it up further on its 5 nanometer node in 2020. Intel's first EUV process did not reach products until 2023. So TSMC had about four more years of experience with these machines. So yesterday we were at the research lab and we're getting a preview of 2D materials and CFET and erythenium interconnects. connects. And I'm curious about how you decide whether that technology is mature enough for the next node. One thing that did also come out of 10-Ender is we started to define a set of maturity metrics. And so we use those maturity metrics in a process, which you call phase gate, where we would say to go from pathfinding into development, these are the criteria that we need to go hit. And there yield criteria defect criteria performance criteria And we need to hit those in order to move to the next set of the flow And if there something that doesn make that then it misses that And it goes on to the next technology And we focus on the items that are ready and we can run and put into a process. Because one of the key things is staying on schedule. Staying on schedule is hard partly because new transistor designs take decades to mature. Modern trip transistors evolved from the planar MOS transistor, demonstrated in 1960. The history of transistors since has been the progression from two dimensions into three. Each development that Chris goes on to describe, from FinFed to gate all around, is a step in that progression. So it'll help to first look at a basic transistor and how its parts have changed over time. A transistor is basically a switch. When it's turned on, it allows current to flow between its two ends, which are called the source and the drain. A piece called a gate sits on top of the silicon between the source and the drain. Applying a positive voltage to the gate turns the switch on, because the positive voltage pulls negatively charged electrons in the silicon beneath up towards the gate. However a thin layer of insulation stops them from actually reaching the gate So the electrons collect just beneath that insulation and form a thin conducting path from the source to the drain This is called the channel Remove the voltage and the electrons disperse, the channel disappears and the switch turns off. As transistors shrank, the source and the drain got so close together that current could flow through the channel even when the switch was supposed to be off. We needed a better way to control the channel and prevent current from leaking through. The fix was to give the gate a tighter grip on the channel by touching it from more sides. In the original planar transistor, the gate only touches the channel from the top. The FinFET transistor squeezes the channel into a thin vertical fin of silicon. The gate drapes over the fin, so it controls the channel from three sides. The next progression from there was to cover not only the top and the sides of the channel, but also the bottom. This technology is called Gate All Around, and it slices the channel into thin ribbons, each of which gets completely wrapped around by the gate. But getting Gate All Around to work required new materials and new manufacturing steps. To build these floating ribbons of silicon, you first sandwich them between alternating layers of a temporary placeholder material which holds the space where the gate will eventually go We use a placeholder because the materials in the real gate wouldn survive the processing that comes after which involves baking the way forward at around 1000 degrees Celsius Once these hot steps are done, chip makers etch away the placeholder, leaving the ribbon suspended. Then they fill the gaps around every ribbon with a thin coat of a special insulator called a high-key material, whose purpose is to let the gate pull more strongly on the channel, And on top of this material, they put the metal of the gate itself. FinFET was demonstrated in a lab in 1989 and reached volume production at Intel in 2011. A gate all-around transistor had been demonstrated a year earlier, in 1988. But Samsung didn't begin producing gate all-around chips until 2022. So these ideas, FinFET and gate all-around, were developed around the same time. But they reached production a decade apart. I wanted to ask Chris why it took so long to get to this current gate all around technology maybe you can walk me through then the process of getting into high volume manufacturing I want to understand concretely once you have an idea that hey we're gonna make the channel smaller we're gonna surround it all the other problems of material science and figuring out how to not destroy the the gate how do they actually get figured out why does it take so long? Gate all around is a good example of [10:00] Because back in the 90s, we knew of this idea, but we knew there was going to be these problems on how you put this into high volume manufacturing. And at the same time, there's other things. Like high K metal gate, there's a strain silicon, there's finfets that are out there. And so it's kind of like, when's the right time to go and tackle those? Well, you don't want to tackle something before you have to. And so if you have these other things that can drive performance, you would go and do that. We went through this path where we did this. We did strain silicon, high K metal gate, we did finfets. And then it became, well, we need to do things further. How do we get there? go and start tackling some of those issues that you have and you're right now you have to look at how you put high k metal gate in with gate all around um so it's that innovation that takes time sometimes it's you need new materials sometimes it's you need a different uh tool in order to be able to do some of the things that you need to go do uh and that requires invention from the tool vendors you have to go to the tool and say hey i need a tool that can do xyz i need a gas that can you that has this characteristic to it. All those things take... time. And some of it's iterative where you have to run a gate all around transition. You say, oh, well, that didn't work. Let me figure out what was wrong with my hypothesis. And Try it again with some different structure. How is the nature of... R&D changed from the era of just making planar transistors smaller and smaller and just getting the benefits of Denard scaling to the world we're in today. Is it just a totally different kind of R&D process? Where previously you were just like, let's make things smaller, smaller, smaller. Now you're going to look at all these other facets of performance at the same time and improvements in size don't come as easily. Walk me through whether there was some crucial change in the R&D process at that point. If you look at the 80s and 90s, yes, it was driven really by Denard scaling, lithography. We just make things smaller, transistors got faster, they got more reliable, and it was very predictable cadence. When we started to hit 2000s, what we saw was that's not good enough anymore. We need to do something different. And to me, it became this golden age of innovation. For each technology node, how are you going to provide... more scaling how are you going to provide more performance and so it drove things like strained silicon it drove high k metal gates it drove fin feds it go gate all around it drove backside power these are things that are you know were in the 80s and 90s you would be like oh no we're not touching any of that because we just continue to have the same process flow we just scale it scale it scale it but uh but that's really for somebody like me who's a transistor junkie uh it's it's You can bring in new materials. I mean, just look at the number of materials we used to use in the 90s versus materials today. It's probably gone up 10x. And there's a lot of innovation. There's atomic layer depositions. You know, I mean, just you're controlling atom by atom this stuff. So it's changed a lot how you approach the process as to before it was try to not change anything. To now, it's like take the sledgehammer and start just tearing the thing up and come up with some new idea. For 14A, Intel is using a new kind of lithography machine. High NA EUV. It uses the same extreme ultraviolet light as today's EUV machines, but changes the optics. NA, or numerical aperture, is a measure of how wide a cone of light the machine's mirrors can focus onto the wafer. The wider the cone you can focus, the smaller the spot that your light can carve. Standard EUV machines have an NA of 0.33. High NA widens it to 0.55. you 1.7 times smaller in a single pass. When features are smaller than the lithography machine can print, chip makers have to split the pattern across several passes, each printing a different set of features. The most tightly packed patterns can require two, three, or even four passes. Each additional pass takes up valuable time on a machine that costs around $200 million, and it introduces another opportunity for defects. High-ending machines cost about twice as much. but they can reduce the number of passes that are needed. So the question which determines whether they justify their higher price is how much more time they save and how much they reduce the risk of defects. Now you guys are using high-N-A UV tools for 14A, whereas TSMC has said that they don't make economical sense yet for them. How do you decide whether the next litho tool is... the one that is ready to adopt or not. Yeah, and Hainé is a good example of where, because of the architecture of our technology versus TSMCs, we make different conclusions off of the same tool set. We use backside power. That means that you actually alleviate some of the pitfalls. [15:00] requirements you have on the front side. And that allows you to print that directly with high NA. TSMC has to run very tighter pitches because they don't have backside power and they can't do that with high NA so they have to use double patterning EV. So it For them, it's not very helpful. For us, it is very helpful. Now at 14, we've left it as an option, and it's something that we'll have a discussion with the customer on because there's some value proposition of it. There's some complexity that it adds. with a signal from another. In the past, all of these power lines and signal lines had to be crammed together on top of the transistors. Intel's newest process moves these power lines below the transistors, to the back of the wafer. This frees up space on top, so the signal lines don't have to be packed as tightly. This change makes high NA worth it for Intel. Without backside power, the wiring is so tight that it would require multiple passes to print, even with high NA. Outside companies can now commission Intel to manufacture chips that they've designed. They follow Intel's Process Design Kit, or PDK, the menu of what a given process can build, and the rules for building it. Do you need to lock that into your PDK right now for customers who are planning on developing on 14A? It's an option in the PDK today, and we're handling it as a customer-by-customer discussion that we have as to whether or not they want to go down that path or not. So for 18A, there was public reporting that there were delays or issues with the PDK such that some instructions didn't work and it was difficult for people to use your foundry to build their chips. Tell me about the process of Intel. becoming a foundry and then having a PDK that other customers can use to make whatever chip that they're making as well? There's definitely a learning curve to how you become a foundry, and that's something that our competitors have gone through as well. PDK is a good example of that. For decades, we've been an IDM, and we've gone to our product teams, and we've shown them our transistor data, and we share that data back and forth, and we haven't had a formal PDK type not having a PDK. And so there's definitely a lot of feedback we've got from the customers as to what they expect for quality and maturity of the PDK, what sort of information that they want to see in there. And so we've tried to incorporate that into making sure that, hey, we have a PDK that meets our customers' requirements. And I think that's where we've ended up is that we're starting to get PDKs that have this. And 14A will have that from the get-go. It has very high quality a dot nine versus a one dot o. And we're constantly going through and taking customer feedback and incorporating that into the quality of our PDPK. For most of its history, Intel's fabs made only Intel's chips. That could be part of what allowed TSMC to gain an edge. Serving many customers gave TSMC more wafers to learn from, more revenue to reinvest, and more pressure to hit deadlines. Basically, all enterprise customers have a shared set of product requirements that you have to meet if you want to even start talking about doing business with them. These are things like SSO, so employees can log into your app with their company accounts, or directory sync, so that whenever someone leaves, their access gets shut off automatically. These features are harder to get right than you think, and the risk reward for building them in-house doesn't really make sense. A slightly better version of SSO probably won't accelerate your growth, but a broken one will definitely stunt it. versions of all the most common enterprise features things like sso skim rback audit logs and more work os also has versions of these features that are purpose-built for agents so they can log in grab the right permissions and take actions within your product all of these features can be plugged in with just a few lines of code so you can add them and get started selling to enterprises. OpenAI, Anthropic, and Thinking Machines, as well as more than 3,000 other companies, all rely on WorkOS to meet their enterprise requirements. If you want to join them, go to workos.com and tell them that I sent you. If a butterfly flapped its wings in the 60s, could you imagine a world where gator all around is not even a word people have heard of, an idea people are familiar with, but people are thinking of an extremely different branch of the tech tree? And how far down the tech tree do you think things could be totally different? Could it be like we're not even using copper? about these type of things. Backside power, that one's pretty out there. I think even in the 90s, the idea that you're gonna strip off the entire silicon substrate [20:00] Put lines on the back side. That one is probably something that's a little bit out there. Copper. Of course, copper wires are the best, so I don't know how you would end up somewhere else besides copper. I think for some of the very tightest pitches, I think it's inevitable that you will replace copper. That's a good example of where you will have another material that will come in there. But for the larger lines, I think copper is about where it's at. I think that once you start to do gate all-around transistors and you do backside power now you start to enter a very different regime because now you see it's not hey there's just some substrate and you stack everything on top now you've got a transistor which is floating in interconnect and you're like okay well why don't i have transistors interconnecting more transistors more interconnect you know this whole 3d stacking that we now do with just discrete chips that we stack on top of each other now you're like why can't I just build an entire structure like this yeah you see it with you know memory NAND DRAM you know they have some incredible 3d structures NAND already does it DRAM talks about it but I think that DRAM inevitably is gonna go there too so a lot of people say oh no we not gonna do this because hey we can do it in the next five years Well come on Let put a larger timescale on this Let put 10 years 20 years in 2045 Do you think you could do it? And now you start to say, oh, yeah, I could see us having some pretty exotic structures at that point. So we limit ourselves by what we see as possible in the next four years. Because, you know, as I've always said, you know, when people say, hey, you know, how do you see technology scaling going? Yeah, we have visibility about four years. And then you get out to that four years and you go, yeah, I think there's something we can do another four years out of that. And you get to that four years and you're like, yeah, I think you can do something. But if you start to talk about 10 years, yeah, it becomes hard to say what it's going to be. Chris's idea of building upwards could start with the transistors themselves. Chips use two types of transistors called N-type and P-type, which work the same way, but with the charges reversed. Nearly every circuit is built by pairing them up. Today, chip makers build them side by side. The next step is to stack them directly on top of each other in order to save space. In principle, that fits twice as many transistors into the same area. This design is called a CFET, short for Complementary Field Effect Transistor. But every extra layer adds manufacturing steps and costs and also leads to heat building up that doesn have a clear way to escape Because logic consumes more power than memory you can do stacks of dram that make hbm or you know 3d nand as easily with logic because of the heat issue is that the fundamental issue then over the long run is how you so there's so there's there's three things that you have when you try to say hey what limits compute okay it's how fast can you do the switch yeah so the frequency of the device how much power does it take in order to do that switch? So the power efficiency of it. And the second one is, how do you dissipate the heat that was generated by doing that switch? And that's the thermals piece. And I think the thermals pieces, and these are not new problems. You can go back 20 years and you can see articles on these three things. And so the question is, yeah, thermals, how do you deal with that? Particularly when you start to talk about these 3D type devices, I think that there is a need for that sort of system level analysis and simulation tools. I think we're at its infancy. because we've just started to look at this. But it is a limiter and it will be a limiter, but, you know, again, these are problems that we can go solve. The problems respond to work, but engineering time is finite and so are the wafers for experiments. Deciding where they go across thousands of problems is itself one of the hardest parts of bringing up a node I sat in on one of Intel Hot Topics meetings where those decisions get made Okay, I'm here with Kevin Fisher, who was laying down the law this morning at the Hot Topics meeting where you guys were discussing how you're improving 18A and 18AP technologies. And people would come to you with these different experiments they were running, different ideas they had for improving yield and for improving performance. And then you and your integration engineers would tell them what data you needed, tell them how they should proceed, tell them how you think you can move things faster. I want people to have a sense of the culture at these meetings. So one thing that I found striking is just that there's, you know, this is bottlenecking your most advanced node. You want to practice to happen fast. And so you kind of lay down the hammer. I would say the average engineer doesn't understand the stakes or the urgency of how this is going to impact, you know, Intel's bottom line, how it's going to impact our customer. They just have no visibility to those issues, right? So they will typically have a certain set of criteria that they want to go capture. They'll hit boundaries of, you know, I asked for something and someone said no, and, you know, I'm done. [25:00] I guess I can't have this thing that I asked for. One thing you learn in this industry is that you will never have a complete data set. If you want to wait for a complete data set, you've waited too long. It's already too late. So a lot of what I end up doing in those meetings is I decide how much risk we're going to take on a certain decision or not take on a certain decision. And you need to say, look, do we go now? Do we start risking production? Because you're risking the bottom line. You're risking revenue. I'm worried you're going to put me in the light of being an ogre because I'm putting the hammer down on you. That's a great reputation to have. It's really conveying urgency. Yes. Every day counts. Yeah. Can you walk me through a particular issue that might come up? Well, one of the examples you saw this morning, which is epi nodules. Epi is short for epitaxy, which means growing new material on top of an existing one. Chipmakers flow gases over a heated wafer, and the gases leave atoms on its surface. The crystal structure of the material underneath acts as a template. Each new atom lines up with the atoms below it and the new layer continues the same crystal Chipmakers use epitaxy at several stages of making a chip In the step Kevin describes they use it to grow the source and the drain as small crystals on either side of the gate So during the deposition of our epitaxy, we get abnormal growth, like a tumor, right? It's going super fast. And that causes problems because one epi will short to the wrong epi and you get transistors not working. And then you've got to narrow it down to how are you going to fix it? For the past decade, Intel's chips have had this feature called processor trace. When you turn it on, it starts recording all the code your program runs, and it captures enough detail that it can go back later and reconstruct every single function call. Most companies don't need that level of detail, but Jane Street does. They need to investigate specific fleeting moments in their trading systems, things like a delayed response to a network packet. Those events tend to be too brief for most debugging tools to catch. So when one of Jane Street's engineers noticed Processor Trace, he started playing around with it. And then he and a summer intern turned that exploration into a new tool called Magic Trace. Magic Trace leverages the output from Processor Trace to give Jane Street a history of every function call leading up to a specific moment of interest This project was completely bottoms It started just as something that one engineer thought would be valuable And now traders and developers across Jane Street use Magic Trace every single day If you want to work somewhere where you trusted to pursue the ideas that you think matter most Jane Street is hiring researchers and engineers. Go to janestreet.com slash thorkash to learn more. One of the pieces that you observed this morning was a special clean that we were looking at, which would eliminate the nodule, right? So the nodule would deposit and then we'd get rid of it. Some of the other discussion was, well, the source of the nodule, get rid of the source of the nodule, right? So how do you decide what – there's some issue. How do you decide what the source of it is? For the most part, we work highly parallel, right? So how do you decide? It's not always evident what the easiest way to fix the problem is. So you work on all the potential fixes. And sometimes it's not the one you expect first. Once we've identified it as a primary problem for the technology, that's where this Hot Topics meeting gets involved. And that's how we align the resources into those engineering teams so that we can accelerate the work. You said there some fast process where wafers can move through faster if they bottlenecking some experiments So we have a tiered system of what we call hotboxes in the factory And every grade of hotbox goes a little bit faster And it just how the factory prioritizes that particular lot, that block of silicon that's running through the factory. So our highest grade of hotbox, hotbox one, races through the factory. It gets priority at every single tool, but it's a drag on the entire factory. If you had a factory person in here, they don't like using, playing that card because you're ending up using the tools inefficiently so that you can go super, super fast. Think of it as a highway and you set aside that one lane for the carpool, right? Which everyone could use, but you're saying, okay, it's just a carpool. That's our hotbox one, right? Everyone clear out of that lane except for that one experiment. And that one experiment races down the highway. Kevin's job is deciding what goes on the production line now. But the day before, I went to Intel's research lab with Jack Cavalieros to see ideas that aren't ready for the node yet. We started with wiring. A transistor is only useful once it's connected to others. And on a modern chip, that takes more than a dozen layers of metal wires stacked above the transistors, called interconnect. These wires are made of copper, and as they shrink, copper starts to run into trouble. Intel is exploring a replacement. [30:00] Ruthenium. Ruthenium has higher resistivity, so why are you guys exploring Ruthenium for the future? So interestingly enough, as you scale the dimensions of those copper wires, you run into challenges. For example, copper requires typically a liner in order to deposit the copper to fill those lines. Ruthenium is very different in that regard because it's a material that we can actually etch. And as such, by etching it, we don't need that liner. So now you scale those very fine dimensions... And if you can trade off that resistive liner, With no liner, Ruthenium starts to win. So there is a crossover point that ruthenium will have much better conductivity, better resistivity than copper. And that's roughly in the 20 nanometer pitch range, which means if you can imagine half of the pitch is your metal line, and the other half is the dielectric that isolates. So what is the liner? The liner is, think of it almost like a glue layer or a transition layer that we need. in order to deposit the copper and have it stick and make that connection to the copper lines below it. These are all interlocking copper lines that interconnect to each other. But every time you deposit copper, you've always had a liner underneath it. And in the past, that liner may have been a significant portion of the entirety of that conduction path. But over time, we've scaled it, made it thinner. And so, Cockroach comes back into play as a contender. One thing I'd be curious about to know is how you decide that a technology is mature and ready for high volume manufacturing. So With 10 nanometer, you're mentioning you guys moved on from copper to cobalt. And there were potential issues with that. How do you decide that this technology is going to work at scale? So the integration of these materials into such a complex system as the transistor ecosystem involves many, many different components. The scalability is one part, but its ability to integrate is another. At the time we made a decision for Cobalt, it was the forerunner. The results were stronger at the time. But as we work with our ecosystem externally, the vendor ecosystem that provides these materials and the tools that we integrate them with, We find solutions down the road That may bring copper back in line as being the stronger of the two. And that's exactly what happens. Every technology that we go through we will evaluate multiple options. And as we... get closer to our time horizon for delivering a manufacturing-worthy product, we have to make a decision. And the leading option at the time was cobalt, now it's copper again. And perhaps in the future, it'll be a ruthenium. I'd love to get your thoughts on CPAT. Basically stacking the transistors on top of each other. What is progress like there... Can you keep making more and more layers? Is it just two? Can we go three, four? How high can you get? Yeah, so that evaluation of CFED is currently underway. not just by us, by our competition Labs externally are looking at it. It is the ultimate in stackability. We're taking transistors that had to be compressed more and more, and we're relaxing that in some ways because we're going to stack them on top of each other. But the act of stacking does not mean that they're not interconnected. What used to be connections on the top or even on the bottom, as you've seen from our press release, now has to go vertically in between the transistors. And that's a new challenge, because the aspect ratio of creating trenches and filling those trenches becomes more and more difficult. So it's not as straightforward as stacking the transistors because you still have to think about interconnecting them. Is the issue there the etch to get that deep pull? Aspect ratio for the etches is a big part of it. We're working with our vendors to evolve on that. But it's also what you fill those very tiny spaces with. Because filling... can sometimes leave... air gaps or holes that never really fill And that's not ideal. I assume there's a version of CFED that works inside this lab. What is the kind of wafer or process or whatever that is working right now? Then what's the next step? What's the next step? What's the next step until it's... inside the full high volume process. Part of the process of evolving these technologies, especially something more complex like an architecture, not just a basic chemistry or material, but a full architecture like CFET, is that we have to make short-loop vehicles that can give us faster turnaround. The normal manufacturing process can take a month or longer to complete the thousands of steps that it goes through. Our goal here is to take unit cells of that process and qualify them. So we take advantage of short loop vehicles that can give us electrical parameters, chemical parameters that can resolve some of those challenges, those speed bumps, And once we've resolved them, then we combine them into a more complex test vehicle. So what you would find in here [35:00] Something very simple. You might be making a diode, you might be making a capacitor, which are components of the transistor. And as those evolve and become stronger, better performing, you combine them to make the next stage, which might be the transistor itself. So in the CFED example, you might not choose to do four ribbons on top of four ribbons. You might just choose to do one-on-one. Because naturally, the aspect ratio of dealing with something that much taller is becomes more and more challenging. So we would have a simplified version of a CFET, which has only one wire for the NMOS and one wire for the PMOS, And that simplifies our job, but it still helps us evaluate the stacking of devices and how they will interconnect. But are the feature sizes here as small as they will be eventually, or are the feature sizes bigger? Oh, absolutely. In some cases... At least a small. For example, you've heard of 2D materials These transition layer dicoc collagenides, as they're called. They're very, very thin materials. They're essentially one monolayer of atoms that we deal with. Those depositions can happen in this lab. We can evaluate those films in terms of conductivity, our ability to contact them. our ability to modulate that conductivity, which is what the transistor does. So yes, we do. have the ability to not only deposit films that are very small and thin, to the atomic scale, but also print very small features. We have EUV technology that can or eBean technology that can allow us to print very small features similar to what we will eventually make in production. I don't understand... intuitively lacking the context in this process. why that you have the features that are as small for working CFAT right now. Yes. Why will it take 10 years for it to be in my phone? What is, I understand that there's like a process, but why is it such a, The answer is slightly different when you're dealing with an architecture like CFET versus a novel material. Materials have, of course, the challenges of being deposited, etched, removed, their compatibility with other layers above and below, all those things have to be researched first before you put them in a production line. An architecture may seem like a simple evolution. Oh, you're making... Nano ribbon transistors next to each other, what's wrong with just stacking them? But the act of stacking them, of course, increases the aspect ratio for etches, depositions, cleans, And the technology may simply not be ready yet. But if you've already made it here, There's a version of the technology that's ready, right? Correct. So we've made a simplified version that may not be an advantage over our current side-by-side technology. of nanorubins. but we need to evolve it to make it maybe two nanoribbons, or to add the right type of metals and dielectrics in order to extract the maximum performance out of that device. Got it. So it's like a long tail of... There's a thousand different steps that all have to come together in a very... unique way to make the performance compatible or actually supersede the prior technology. Where do the ideas tend to fail? You have like 20 ideas that are like 2D materials. What is the kind of way in which you're like, this is actually... not worth pursuing further? Sometimes the idea becomes something that we discover fundamentals about the material that will be incompatible with the rest of the processing that we do. At first, the first level of experiments may simply be very simple depositions and you say, "Okay, I can deposit the film, I can look at it, I can measure it." But the moment I try to make a contact to it, nothing sticks. It could be something fundamental as simple as the adhesion of the Next step in the process is simply has no way to adhere to the material. So you may rule out a material because of something as simple as that. More complex. challenges might be The subsequent processing may have gaseous interactions with with downstream steps. So for example, I've deposited the film, I've capped it with other materials, but they're not hermetic. And so, my third or fourth or fifth step in the process may actually still interact with it and change its properties. That makes it unstable. And now we have to find better hermetic sealing... for that process. And if you don't find a way to control it, then it's a dead end for us. Stacking transistors is still in the research lab. Stacking whole chips is already in production, and it tackles a different problem: how separate chips communicate with each other. Modern computers are divided into multiple parts, each optimized for a different task. [40:00] For example, NVIDIA's Blackwell Data Center GPU joins two huge processor chips and surrounds them with eight stacks of high bandwidth memory. These chips have to constantly send data back and forth with each other, and in AI, the speed of that traffic, not the raw computation itself, is often what limits how fast the workload finishes. connections. This is the area versus perimeter problem. As transistors become denser, a chip's ability to do computations increases faster than its ability to move data around. The industry has known about this problem for years, so multiple technologies have been invented to address it. The completed circuits must undergo two last operations. Bonding and packaging. Once a chip is made, it still has to be connected to other chips and to the rest of the computer. That step is called packaging, and it has changed a lot in the last few decades. At a high level, you can think of the evolution of packaging like this. Initially, chips were laid out side by side. Wires connecting them went out the side of one chip to another. To allow for more communication density, the industry introduced a shared piece of silicon called an interposer for multiple chips to sit on. that runs directly through the interposer. This type of packaging is often called 2.5D. Another way to increase connection density is to bond chips directly to one another. This allows for shorter connections between chips, but the early versions of this idea use solder bumps, which are bulky and increase resistance. It would be better to skip the solder and fuse the signal wire connections of the two chips directly to each other. This is called hybrid bonding, and it is history is investing in the most. Hybrid bonding works by aligning the copper interconnects of one chip with those of another. Then these chips are pushed together and heated so their interconnects expand and bridge the gap between the chips. This process makes the insulating surfaces around the copper bond as well. And so by removing the solder bumps, you end up with much denser connections. But the reason this technology is only now entering volume manufacturing is because it took a while to iron out the alignment and defect challenges that it introduced. In the packaging lab, I asked a director in Intel's Advanced Packaging Technology Development Group, how they put this into practice. Intel has spent over 50 years optimizing its CPUs for speed. But lots of these optimizations, like caching and branch prediction and speculative execution, reduce predictability. The exact same instructions can take four cycles to execute one time and 300 the next. When you stack billions of instructions together and execute them across multiple threads and cores, these non-determinisms compound into all sorts of hard-to-reproduce bugs. You've definitely experienced this. Antithesis solved this by doing something a bit crazy. They built a 100% deterministic computer. They identified every single door in Intel's x86 architecture where non-determinism could leak in. Network packets, disk screeds, temperature sensors, even time itself. And they either welded each of these shut or slotted in a controlled simulation. This deterministic computer is just a foundation. hardening into minutes. It runs your software through thousands of parallel worlds, injecting faults and intelligently steering each one towards a one in a billion failure that you'd never be able to test yourself. This determinism is what's behind all the other insane antithesis features that I've mentioned over the past few episodes. It's what lets you reproduce any bug in time travel to any point in the test run. Most importantly, it's what lets you or your agents Learn more. Bye. Two different ways you could do hybrid bonding is die to die and die to wafer. Uh-huh. And maybe we can talk about the advantages of both and which one actually practically works better. Sure. So actually around Intel, typically, I think as you're referring to die to die, We typically call it wafer to wafer. So we actually take a full wafer and another wafer and bond them together. That's an approach that's really popular right now in the CMOS image sensor industry. In fact, basically dominates it. And it's being looked at for other things like memory stacking, all kinds of stuff people have published ideas about. One of the challenges with that though is that you need dyes that perfectly match each other. and are perfectly left-handed and right-handed, right? So you have to be able to plon exactly one to the other. So one-to-one die size is a challenge. So If they're not the exact same design device on top and bottom, that's a problem. So wafer to wafer, it's just challenging to make sure that you have wafers that match really well in terms of the sort, right? So sort good array here versus sort good array here. If they match exactly good die and bad die that they all match, I can get 100% yield of that operation of the good dies. But the chances that are very low. It's going to be some randomization of the two. [45:00] And whatever that randomization is, it's just going to be loss of good bonding to bad. Whereas it chipped away for I can dictate the terms, right? I can singulate and have known good dyes that I've tested at the chip level, and then only bond known good to a known good base position. Do you think then ChippedWafer is the way that you'll do hyperbonding in the future? I think we're going to do both. We definitely have the capability to do both. It's really customer and architecture driven. But certainly chipped a wafer in the logic to logic space makes a lot of sense. So you were explaining that going from advanced packaging to hybrid bonding, the size of the pitches is decreasing. How much further could that go? That's a wonderful question. So, you know, historically, like we were saying, 15 years ago, first level interconnect was 130, 150 micrometer pitch. Today in HVM, we're doing 25 micrometer pitch in Fulveros. Here we're doing sub 10. There's already been literature out there. In fact, the biggest conference every year in packaging is the IEEE ECTC conference that happens in May. And there was a paper there this year showing reliability data on a 0.45 micron pitch hybrid bonded device. So you can imagine that's a whole other order of magnitude and density again from where we are right now on HVI and scalability, that's already been proven. So I see a long runway there. Within Interconnect, within a single wafer, how far separated are they usually? So the back end of the fab, you can imagine, like the few layers below packaging, are typically around one micron to a half micron. in size. So if you can push packaging down to 0.5 microns or below, We can start You can almost think about taking layers off the top of the die. And connecting to a lower layer within the silicon to another lower layer within the silicon, right? That's really kind of where the beauty of hybrid bonding happens. You can think someday about even having reduced interconnect layers on both sides that we can bond together and have less total IR drop between the two transistor layers. It's really Kind of cool to think about where that could go once we get into those regimes. Actually, I am very curious about for ai it makes sense why hyperbonding is so powerful because then you can get like higher bandwidth of the memory Absolutely. You're saying with issues with heat and everything. What is the advantage for non-AI applications of hybrid bonding? Excellent question. So there are companies out there that are looking at it for non-AI applications, even in fact in client devices, right? And one of the big things I think that that can help with there is Well, number one, obviously the same raw interconnect density, especially between something like a CPU and a GPU. But the other one is around power. Right. So like we talked about before, as you get to find and find our interconnects, you can reduce the total power consumption in picojoules per bit for that interface So with hybrid bonding, In those applications, you could think about that as another way that package, you can help reduce the total system power budget. Interesting. So then that gives you lots of benefits, right? Lower power, less heat. for the same benefit in terms of actual electrical performance. So far, this has been about making better chips. The other half of the question is how many chips the industry can make if AI labs are willing to pay for far more of them. I'm getting a chance to talk to Pushkar Arande, who is the CTO of Intel. I'm very interested in understanding how The fact that the entire industry has to rely on the same suppliers bottlenecks your ability to ramp up production. So For this EUV tool, ASML produces less than 100 of them a year. Yes. And they don't plan to produce more than 100 a year, even by the end of the decade, or significantly more than 100 a year. And that is to be split between you, between TSMC, between all the memory makers who are ramping up production like SK Hynix. How does that limit your ability to scale up to all this demand? It is a limiter. So we have to make the most of the capacity that we already have installed, and we'll try to increase the output from our existing fleet of tools. EUV or ASML is not the only bottleneck. It is definitely a bigger bottleneck than some of the other tools, but to a large extent, we're seeing all equipment seeing tremendous supply shortage. Even though there are multiple providers of other tools, once you lock into a process flow, let's say 18A, 18A is a mature process now. So we need... a specific tool. We can't just go out, go and get a different tool for the same, for the same. So, so therefore we're locked into that one tool, one supplier. And, um, and so we rely on that. What lessons does this give for 14A in terms of by 2028, it's going to be such a crazy world. Yes. How do you structure things in such a way that you can, you have flexibility in ramping? Yes. Actually the way to do it, and we've been doing it and generally everybody does it is you try to maintain as much fungibility as possible going from one node to the next node. So let's 18A to 14A, maybe you would say 80% of the tool set can be reused. And then of course 14A, for example, would require some new capabilities because it's a denser [50:00] So it would require some unique tools. Do you have a sense of what is the ultimate bottleneck of how many wafers you guys could produce a month, even if you were decided to invest infinity money into doing CapEx? Given the existing constraints, let's say we had to maximize the output from a given footprint of tools, then I think it's incremental because the process today is already yielding pretty high. And if your yield is already pretty high, to get every 1% extra yield is extremely hard because it's already a finely tuned process. Are there enough tools in the world so you could 10x the amount of wafers you're producing at the leading edge? Not 10x, but probably like 2x, yes. That's quite interesting because the AI industry for a decade has been 3x in compute. Yes. Year over year? Yes. And you're saying that that just can't continue? Unless the entire supply chain, starting from the equipment suppliers, their suppliers, their sub-suppliers, unless everybody produces more, you can't increase the output collectively. Just to give the audience a sense of how big the AI demand is and how well it monetizes the products you guys are producing You can crunch the numbers and the numbers seem to suggest that just a couple billion dollars of CapEx on Intel account results in enough chips or the logic for enough chips to produce, say, $100 billion of revenue for the AI model companies. And of course, there's so many other players within that stack. There's also memory and other things. But it's crazy that within a couple billion dollars of CapEx, which can be amortized over many different years, produces $100 billion of revenue every single year. Which seems to suggest that at some point that should percolate down. At some point, the AI labs could just say, we'll just buy everything, produce as much as you can. We'll just guarantee future income streams and stuff. There's early signs that that could actually be happening already. The demand signals are just so high. But I think you were alluding to how the value is accumulating at the top of the technology stack which is essentially what is happening is we move from a fully vertically integrated industry like 30 40 years ago maybe longer to a very horizontal industry where you have foundries you have equipment makers you have their suppliers And today you think about it every hyperscaler is designing their own chips And the scale of the hyperscalers is so large. And some of the, you know, the model companies, for example, and their demand is so high. Yeah, they could easily just like, consume an entire fabs worth of silicon on their own, or multiple fabs worth of silicon on their own. And they definitely have the capital to fund that. So in some sense, we are moving from a sort of a horizontal world, again, to a pseudo vertical world where it's like the, you know, it's not monolithically vertically integrated, but it's kind of virtually vertically integrated. Interesting. What is the nature of economies of scale in this business where you look at how many wafers are the leading edge TSMC versus Intel are shipping, upwards of 3x for TSMC. What kinds of advantages do you get at this point from economies of scale? Or is it that once you reach a certain point, the economies of scale get weaker? That's a very important question. This entire business just relies on scale and economies of scale I mean if you look at sort of all the advanced manufacturing companies out there probably semiconductor foundries, the scale economics is probably the purest. And the reason for that is the fixed cost is just so incredibly high that once you build a fab, like 80% of your cost structure is fixed. And so what that means is every extra percentage of utilization is adding far more in revenue. So therefore, it's extremely important. And we'll fight for every extra percent of FAB utilization, but also every extra percentage of FAB output. As in, let's say I'm making some wafers today and the yield is like 60%. But if I improve the process and the die yield becomes 65% or 70%, it's not a linear advantage. It's like I'm getting way more output for the given footprint. So there's always room to improve the economies of scale. And that's one of the reasons why you're seeing so much consolidation in this business. There's only three foundries left at the advanced node for that exact reason, and just along [55:00] way, many companies just stop manufacturing. I don't know if you've seen, there's a chart where like 40 years ago, there were like, you know, 20 foundries. And, you know, over time, like the number of foundries kept diminishing until today, there's only three. What is the basically then the concrete master plan to catch up to TSMC? Even though TSMC is ahead, there's so much overflow demand at their leading edge, where N3 is now majority AI accelerators, It may be majority NVIDIA alone, that all this demand for CPUs, for other things, which are also, by the way, needed for AI. There's humongous influx and demand for CPUs because of AI. How do you see this opportunity right now where Intel's a few years before, while TSMC is just way oversaturated? Catching up to TSMC maybe has multiple facets. I would say the catch-up that we need to do is in scale. You know, like you said, they're just a much larger wafer manufacturer today than we are, and even bigger than what Samsung is. Caching up in scale will be a slow process, a gradual process. If you meant you know catch up in terms of just the technology I think that you know I think we already there Like you know we might maybe you know a few percent off on performance or power or area density But, you know, this sort of benchmarking of, you know, one foundries ahead or one foundries behind, it makes sense when you're like a whole generation behind or two generations behind or ahead. That's when it makes a meaningful difference in your dye output or your dye area or functionality like power. But if you're within like a few percent, it's really you're splitting hairs at that point in time. Because it's not very unidimensional at this point. It's not just about density. It's not just about raw performance. Different applications require different vectors. So you can be off by a few percent, but you need to be on time. Your execution needs to be such that your yields are very high to support very large and very rapid ramps So that actually is more important than catching up on a few percent in performance or area I was looking at some semi numbers that seem to suggest that in terms of transistor density, 14A, which will come out in like 2028, would it be comparable to N2? Yeah. First of all, I would dispute your benchmarking. But like I said, I think you know, it's important to be generally in the right ballpark, be very predictable. And also, you know, it's not unidimensional in terms of, you know, we don't build one type of transistor, let's say 14A or 18A. You build a few different types of transistors. Let's say there's a low leakage transistor, there's a high performance, you know, high drive current transistor, you're building SRAMs, there's a high density SRAM, there's a high performance SRAM, There's many other functionalities, like some analog circuits, RF circuits. So it's the sum of all of those that makes the technology competitive. I guess that makes the CapEx you do right now even more important. So right now, or like TSMC is on track to do 50 billion in CapEx, around 50 billion in CapEx this year. You're on track to do around 20 billion. Yes. But if the tools you buying right now will determine who can service all this crazy AI demand that coming up it makes the difference in CapEx even more important for like US versus other countries Yes, very much. It's a little bit of an unfair comparison between us and TSMC today, just because today they're a foundry for basically everybody. And we're largely a foundry for Intel. We'll become a foundry for others. so in in due course our capex will also grow intel started as a uh drm business in the late 60s and then you guys are producing drm which you sold off a couple years ago you sold off uh your flash business yes um yeah thoughts on that given uh for context for the audience these are now multi-trillion dollar industries because of the they've just you know exploded as a result of AI demand for them. Yes. I mean, clearly, in hindsight, probably not the smartest time to sell off a flash memory business. There were good reasons why we did that when we did. Clearly, you know, nobody could see this demand, this enormous demand. But no, today, I think, I mean, essentially, the world will eat up as much demand. [60:00] compute as can possibly be made, and it'll eat up as much memory as can possibly be made. I would argue that the supply crunch is larger for memory today than it is for compute. So can I summarize what it seems to me the takeaways from your projections are? And you can tell me if that's correct. Yes. Marginal production can increase actually very fast, you know, on the scale of 12 months. But the amount of increase up till the end of the decade is extremely limited. Yes. Production could be higher next year than what people are forecasting. But production in 2030 is not going to be significantly higher than what people are forecasting. Unless the entire supply chain ramps up production very quickly. I mean, we're already in the middle of 26. So there's, you know, only not that many years until the end of the decade. the lead times, you know, let's say you place an enormous order for tools today, right? And you're looking at, let's say, 18 months to get those tools, you're already into basically 28. And from that point on, if you have to build a new shell, build a new fab, I mean, you're basically looking at the end of the decade. I think it'll be interesting to discuss the partnership you guys have with Elon on TerraFab. What's going on there? Well, I think so Elon's publicly talked about his his desire to to build a fab. We either build the TerraFab or we don't have the chips. And we need the chips, so we're going to build a tariff out. Sort of the same thinking, you know, I think he's seeing just a... enormous increase in demand for silicon, for compute and for memory. And I think he came to the conclusion that his own businesses are going to require a lot of silicon. And so he, you know, he thought maybe he should just do it all on his own. Unlike building a car, for example, the This is such an intricate and complicated process. We thought we could work together to help accelerate his progress. bringing up his fab. But because of the bottleneck of the tool level, it seems like the net amount of silicon in the world won't increase. It's just that maybe if somebody were to start a new fab, they would get access to guaranteed supply in a way that they wouldn't have if they're working with another person's foundry. It's actually not just tools. I mean, a fab does require a lot of power, a lot of water, like a lot of consumables. There's many other... input variables as well. But those can be scaled in the way that like tools cannot. Yeah. Yeah. Some more than others, but yes. But yes, in one sense, yes, we need a lot more equipment. But it is true. I mean, we also need a lot more just raw fab space, raw clean room capacity. So if you think of a foundry like Intel, which has to... build these expensive facilities, buy expensive tools. I wonder what you think the economics of that fundamentally could look like, whether it could get more economical, whether it could scale faster. capital heavy business. And if you look at the, if you just plot the, you know, how much does it cost to build a fab? And if you just over the last, I don't know, 20, 30, 40 years, I think it's like doubling every four to five years. Even inside the fab, if you look at the cost to do lithography, which is the most expensive module, just patterning, that itself is doubling like more than that at and all its associated equipment, it's like, $400 million, right? And so what does that mean? If that rate were to continue, if you just look, draw the line and say, okay, does that mean like four years from now, like cost of patterning is going to be like, 800 billion, right? Doesn't, you know, 800 million, it doesn't really make sense, right? I think that a very interesting thought exercise to do is to say... You know, are there things that could be just very radically different that we could do today that we perhaps couldn't do? 20 years ago. This is a very risk-averse situation. industry for very good reason, for exactly that reason, right? You put in like tens of billions of dollars and you really don't want to take any risks. So you want to keep doing things the way they've been done for literally decades. And this is not just true of semiconductors, but like everything really. But if you've just kept on doing that for decade upon decade, many things just become like, you know, you just become indoctrinated, right? And I mean, there are who just come in and they're taught, this is how the fab, this is the process flow. And they just take that as gospel, right? That's just how it is done. But is that really the best way to build a chip today? [65:00] It's a really valid question. - I'm very curious what you're hinting at, 'cause it could be anything from, you know, we can figure out ways in which you use fewer lithopasses and economize on this expensive component to like, maybe we need to rethink the transistor. Where, what is the level? I think all of the above. Transistor architecture and evolving... Just the silicon transistor has continued to evolve over 30, 40 years, and that will continue. So, right, you've seen the evolution from, like, the planar transistor to FinFETs to now gate all-around transistors. There'll be more. That roadmap is pretty... It exists, and it's pretty well-defined. A lot of people working on it. But there's things like, do you really need a clean room today? Do you need the infrastructure to be as sophisticated, as complex as it is today? Surely one can run an experiment where people are eating hamburgers and smoking cigars in the research lab and see what happens to yield. That would be a great experiment to run, but no incumbent like Intel or TSMC or Samsung. I mean, nobody would want to just willingly do that. So that's what I meant really by this. It's a very risk-averse business for good reason. Every one day loss in productivity is like, I don't know how many dollars, right? But you save so much money and not having to build clean rooms in the future. But it's really the fear of the unknown, right? So nobody is going to willingly take that risk. But that's why I think sometimes it's good to just start with a clean slate and rethink everything. And it's like, okay... These things, you know, same thing applies to like, you know, chip design, by the way, right? Many of the ways we do CPU design were probably locked in like, you know, 30 years ago. Does that mean it's this... smart to still do it the same way? Probably not, right? But this is a very complex problem. You know, chip design is like easy to, it's fairly low, you know, I guess the capacity to take risk is maybe higher. This one, less so. But given where the economics is today, I think it's a very valid question to ask, you know, like, Maybe that's a smarter way to do this. To close out, maybe we'll start off at the same question we began the interview with, which is how does Intel respond to this crazy AI demand that's incoming and has already arrived? It sounds like what Intel ought to do if the ultimate bottleneck is you guys already have these foundries, you guys already have the ability to expand these foundries. But what you will eventually lack is the tools from upstream in the supply chain to just raise as much capital as possible right now. The same way that NVIDIA has locked down memory and other components for reportedly hundreds of billions of dollars worth of commitments that it's made. Yes. Intel should maybe do the same thing, make all these commitments so that as over the coming years, the U.S. is in good position to have the bulk of semiconductor manufacturing at the most advanced levels happening here. you're saying we should be buying a lot more tools, right? Yeah, because it sounds like it's just like, well, in a couple of years, otherwise, you'd just be in a position where you're like, oh, man, we're gonna be making trillions of dollars right now. But all the tools are in Taiwan. Yes. I mean, no, that's a very, very valid question. Had we known what we know today, we would have bought invested more like a year ago. Knowing what we know now, I think we'll be investing more.