Intel Sees Tool Bottlenecks Capping Chip Expansion as AI Demand Surges

Dwarkesh Patel

Global chipmaking equipment constraints leave foundries able to only double leading-edge wafer output despite AI demand tripling yearly.

AI-assisted summary of What will computer chips look like in 2045? — original source. Check the original for full context.

Source published: 2026-10-22

Key ideas

Intel executives evaluate that global semiconductor tool supply chains could support doubling leading-edge wafer output, but cannot support a 10x expansion to match AI compute demand growing roughly 3x per year. (50:05)
High-NA EUV scanners costing $350–400 million are economically viable for Intel's 14A node because backside power widens frontside wiring pitch into single-exposure range, whereas TSMC would still require double-patterning. (13:13)
Intel is developing liner-free ruthenium interconnects to replace copper below roughly a 20nm pitch, avoiding the severe resistance and electron scattering caused by diffusion barrier liners in ultra-thin trenches. (29:30)
Packaging interconnect pitches have dropped from 130–150 microns to 25 microns in Foveros production, with sub-10 micron hybrid bonding converging directly with fab back-end wiring to bypass upper metal layers. (45:30)

Detailed notes

## Background Published by Dwarkesh Patel on YouTube on October 22, 2026, this episode covers a two-day tour of Intel's most advanced semiconductor fabrication facilities and in-depth discussions with its technical leadership. The program explores upcoming hardware architectures like Gate-All-Around transistors, backside power, CFET, and hybrid bonding, alongside an examination of how foundries can cope with the massive demand shock brought on by AI.

## TL;DR The episode provides an inside look at the technical and economic realities of leading-edge semiconductor fabrication as the industry races toward 2045. Dwarkesh Patel tours Intel's fab and interviews key engineering executives to unpack critical architectural shifts, including the transition to RibbonFET, backside power delivery, ruthenium interconnects, and CFET monolithic 3D scaling. The discussion highlights lessons from historical execution delays, contrasting Intel's adoption of High-NA EUV with TSMC's roadmap, while examining packaging innovations like chip-to-wafer hybrid bonding. Crucially, Intel leadership addresses the structural supply crunch driven by AI compute demand, noting that while existing tool supply chains from makers like ASML might support doubling leading-edge wafer output, a 10x expansion is physically gated by equipment lead times and high capital costs.

## Atmosphere & style The presentation is intellectually rigorous, fast-paced, and deeply technical, blending journalistic curiosity with granular microelectronics engineering. Shot on location with animated visual explainers, the conversations with Intel leaders carry an air of pragmatic candor rather than corporate PR, openly confronting past failures like the 10nm delay alongside current high-stakes bets on 18A and 14A. The resulting atmosphere feels like an urgent, unvarnished debrief from the physical frontier of Moore's Law, balancing awe at atomic-scale precision with sober realism about the geopolitical and manufacturing bottlenecks constraining the AI boom.

## Bulletin - [50:05](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3005s) Intel executives evaluate that global semiconductor tool supply chains could support doubling leading-edge wafer output, but cannot support a 10x expansion to match AI compute demand growing roughly 3x per year. - [13:13](https://www.youtube.com/watch?v=frYSOKvNiiE&t=793s) High-NA EUV scanners costing $350–400 million are economically viable for Intel's 14A node because backside power widens frontside wiring pitch into single-exposure range, whereas TSMC would still require double-patterning. - [29:30](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1770s) Intel is developing liner-free ruthenium interconnects to replace copper below roughly a 20nm pitch, avoiding the severe resistance and electron scattering caused by diffusion barrier liners in ultra-thin trenches. - [45:30](https://www.youtube.com/watch?v=frYSOKvNiiE&t=2730s) Packaging interconnect pitches have dropped from 130–150 microns to 25 microns in Foveros production, with sub-10 micron hybrid bonding converging directly with fab back-end wiring to bypass upper metal layers.

## Key takeaways - [00:00](https://www.youtube.com/watch?v=frYSOKvNiiE&t=0s) AI compute demand growing at roughly 3x annually faces a hard physical ceiling set by upstream toolmakers like ASML, with chip demand exceeding maximum fabrication capacity by 40% to 50%. - [00:47](https://www.youtube.com/watch?v=frYSOKvNiiE&t=47s) A leading-edge node like Intel 14A requires over three years of pathfinding and roughly 2,000 discrete processing steps per wafer in the cleanroom. - [03:22](https://www.youtube.com/watch?v=frYSOKvNiiE&t=202s) Intel's costly 10nm delay stemmed from hyperscaling with DUV immersion multipatterning instead of EUV, prompting strict phase-gate metrics before nodes enter mainstream development. - [06:28](https://www.youtube.com/watch?v=frYSOKvNiiE&t=388s) The evolution from planar transistors to FinFET and Gate-All-Around (GAA) nanosheets was driven by electrostatic channel control to prevent leakage as dimensions contracted. - [13:13](https://www.youtube.com/watch?v=frYSOKvNiiE&t=793s) High-NA EUV tools double machine costs to $350–400 million, creating divergent adoption strategies between Intel and TSMC based on underlying node architectures. - [19:20](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1160s) Backside power delivery decouples power delivery from signal routing by thinning wafers to tens of nanometers and flipping them, relieving frontside wire congestion. - [20:28](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1228s) Complementary FET (CFET) vertically stacks NMOS and PMOS transistors to double density, but creates extreme vertical aspect-ratio etching challenges and severe thermal penalties. - [29:30](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1770s) At pitches below 20 nanometers, liner-free subtractively etched ruthenium outperforms conventional copper because copper barrier liners consume too much conductive volume. - [36:43](https://www.youtube.com/watch?v=frYSOKvNiiE&t=2203s) Transitioning novel transistor architectures or 2D materials from laboratory proof-of-concept to high-volume commercial manufacturing takes roughly a full decade. - [39:45](https://www.youtube.com/watch?v=frYSOKvNiiE&t=2385s) 3D hybrid bonding eliminates solder microbumps by directly fusing atomically polished copper and dielectrics, circumventing the area-versus-perimeter edge-routing bottleneck. - [43:53](https://www.youtube.com/watch?v=frYSOKvNiiE&t=2633s) Chip-to-wafer bonding provides critical yield advantages over wafer-to-wafer bonding by allowing pre-testing and pairing only known good dies. - [53:01](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3181s) Fabs have an ~80% fixed cost structure, making high utilization and percentage-point yield improvements far more economically impactful than marginal PPA advantages. - [59:11](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3551s) Tooling lead times of roughly 18 months cap unexpected wafer supply expansion before 2030, meaning new fab construction cannot solve short-term shortages without additional tool output. - [01:06:26](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3986s) Astronomical capital risks and machine costs doubling every 4 to 5 years enforce deep operational conservatism across incumbent foundries, entrenching decades-old design methodologies.

## Detailed walkthrough ### [00:00](https://www.youtube.com/watch?v=frYSOKvNiiE&t=0s) The AI Demand Shock and the Hardware Bottleneck

The semiconductor industry is currently navigating an unprecedented surge in demand driven by the explosion of artificial intelligence. While AI compute requirements have expanded exponentially over the last decade—roughly tripling year over year—foundries are facing a severe capacity crunch. Semiconductor executives report customer demand running anywhere from 40% to 50% above maximum fabrication limits, an imbalance of a scale never seen before in the history of chipmaking. Sustaining this level of AI progress requires chip manufacturers like Intel to drastically increase the output of leading-edge silicon, which means not only expanding raw wafer volume but also packing far greater capabilities and efficiency into every individual die.

That manufacturing ambition runs directly into physical hardware limits. Production throughput is strictly gated by the specialized fabrication equipment supplied to chipmakers, most critically the extreme ultraviolet (EUV) lithography systems manufactured exclusively by Dutch supplier ASML. Without these massive, multimillion-dollar machines installed and running on the factory floor, advancing production is impossible. To understand how the semiconductor ecosystem plans to navigate this supply-demand bottleneck and what future silicon architectures will look like, Dwarkesh Patel toured Intel’s premier fabrication facilities and met with the company's technical leadership.

[00:47](https://www.youtube.com/watch?v=frYSOKvNiiE&t=47s) Bringing Up a Process Node: The 2,000 Steps of 14A

Dwarkesh sits down with Chris Auth, who oversees development for all processes currently heading toward high-volume manufacturing at Intel. Dwarkesh asks how a future process node—such as Intel 14A, slated for commercial release two to three years out—is systematically developed, tested, and fine-tuned over time. Auth explains that by the time a node reaches this phase, it has already undergone more than three years of intensive pathfinding and pre-work. At the current stage, Intel engineers are locking down the final process window, finalizing the exact toolsets required across the fab, and optimizing each individual operational step.

Fabricating a cutting-edge wafer requires approximately 2,000 distinct processing steps inside the cleanroom. Every single one of these steps must be engineered for extreme repeatability so the fab can reliably process thousands of wafers every week with predictable yields. Yield improvement does not happen by chance; it relies on relentless defect tracking across two core avenues:

- **Inline Metrology:** Automated inspection tools inspect wafers directly during the manufacturing process, flagging particulate contamination and physical anomalies as they appear layer by layer. - **End-of-Line Electrical Testing and Sorting:** Finished wafers undergo electrical sorting to identify circuit failures. When a die fails, failure analysis teams excise microscopic cross-sections of the defect using transmission electron microscopy (TEM) in the lab.

By analyzing these physical cross-sections, engineers identify the exact vertical layers where a short or void occurred. They trace that location back to the specific manufacturing station in the 2,000-step flow and correlate it with inline inspection data to eliminate the root cause. As Auth emphasizes, managing this complexity requires discipline: “What we’ve learned is that you don’t want to do too much innovation in one node, because the more innovation that you do, the more complex it becomes.”

[03:22](https://www.youtube.com/watch?v=frYSOKvNiiE&t=202s) The Lessons of 10nm: Hyperscaling and Phase Gates

Intel's conservative philosophy around node complexity stems directly from the painful setbacks it suffered on its 10-nanometer process node. Historically, Intel drove the two-year cadence of Moore’s Law, but the 10nm process—originally scheduled for high-volume deployment in 2016—slipped until late 2018, causing products to fall nearly four years behind schedule. When Intel announced the delays, its stock plunged more than 15% in a single trading session, while its chief rival, Taiwan Semiconductor Manufacturing Company (TSMC), rallied 13%.

Auth explains that 10nm was characterized by an overly ambitious push known internally as "hyperscaling." Intel attempted to shrink transistor features far faster than the historical rate while relying on existing deep ultraviolet (DUV) immersion lithography tools because next-generation equipment was not ready. To achieve that aggressive scaling without new tools, engineers devised convoluted multipatterning schemes that placed an unsustainable burden on process development and engineering teams. Although 10nm eventually matured into a high-yielding, high-performing, and cost-effective node, the delay cost Intel its manufacturing lead.

The biggest tactical error of that era was concluding that extreme ultraviolet (EUV) lithography was not ready. EUV uses light with a 13.5-nanometer wavelength—roughly 14 times shorter than the 193-nanometer light emitted by previous DUV immersion scanners—allowing fine features to be printed in a single exposure rather than multiple passes. While Intel opted to bypass EUV for 10nm, TSMC leaned aggressively into the technology, entering commercial high-volume EUV manufacturing in 2019 and scaling it widely across its 5nm node in 2020. Intel did not field its first EUV-based production node until 2023, handing TSMC a four-year head start in tool calibration and operational expertise.

To ensure such delays never repeat, Intel overhauled its operational management by instituting rigorous "phase gate" criteria: - Research and pathfinding initiatives can only transition into mainstream process development if they satisfy predefined maturity metrics for defect levels, yield predictability, and baseline electrical performance. - Any exploratory technology—whether 2D materials, complementary FETs (CFET), or novel metals like ruthenium—that fails to meet its phase-gate milestones is immediately pushed to a later node rather than allowed to compromise the delivery date. - As Auth summarizes the core lesson: “Having that predictable schedule is a key piece. You’ve got to figure out how much innovation you can put in in order to meet the customer’s requirements in the timeline that they need it.”

[06:28](https://www.youtube.com/watch?v=frYSOKvNiiE&t=388s) From Planar to Gate-All-Around: The Architecture of Modern Transistors

To understand modern process engineering, one must look at how transistor structures have evolved from two-dimensional surfaces into complex three-dimensional architectures. Every field-effect transistor functions fundamentally as an electronic switch. Applying a positive electrical voltage to the gate pulls negatively charged electrons through the underlying silicon, gathering them just beneath a thin insulating barrier to form a conductive "channel" connecting the source to the drain. Removing the voltage causes the electrons to disperse, closing the channel and turning the switch off.

As transistors shrank down to nanoscale dimensions, the physical distance separating the source from the drain became exceedingly narrow. Consequently, the gate lost electrostatic control over the channel, allowing unwanted leakage current to slip through even when the switch was nominally off. To restore control and suppress parasitic leakage, chip designers had to increase the surface area between the gate and the channel:

```mermaid flowchart LR accTitle: Evolution of Transistor Gate Architectures accDescr: Diagram tracking transistor architectures from 2D Planar to 3D FinFET and Gate-All-Around nanosheets.

subgraph Planar["Planar Transistor (1960)"] direction TB P1["Flat Silicon Channel"] --> P2["Gate Touches Top Surface Only"] P2 --> P3["Vulnerable to Short-Channel Leakage"] end

subgraph FinFET["FinFET (Lab: 1989 / HVM: 2011)"] direction TB F1["Vertical Silicon Fin Channel"] --> F2["Gate Wraps Around 3 Sides"] F2 --> F3["Improved Electrostatic Control"] end

subgraph GAA["Gate-All-Around / RibbonFET"] direction TB G1["Suspended Silicon Nanosheets"] --> G2["Gate Wraps All 4 Sides"] G2 --> G3["Maximum Electrostatic Drive & Density"] end

Planar -->|"Scale limits reached"| FinFET FinFET -->|"Fin pitch limits reached"| GAA ```

- **Planar Transistor (1960):** The classical metal-oxide-semiconductor (MOS) architecture where the gate sits flat on top of the silicon channel, exerting electrostatic control strictly from a single side. - **FinFET (Commercialized by Intel in 2011):** The silicon channel is extruded upward into a slender, three-dimensional vertical fin. The conductive gate drapes over the fin, wrapping around three sides (top, left, and right) to clamp down on sub-threshold leakage. - **Gate-All-Around (GAA) / RibbonFET:** The channel is sliced horizontally into a vertical stack of discrete, suspended silicon ribbons (nanosheets). The gate material wraps completely around all four sides of every individual ribbon, maximizing electrostatic drive current while suppressing off-state leakage.

Manufacturing GAA ribbons requires an intricate, multistage chemical sequence. In the fab, alternating layers of silicon and a temporary sacrificial material (silicon germanium) are grown epitaxially to create a layered sandwich. Because permanent high-dielectric (high-k) gate materials and metal gates cannot withstand the downstream high-temperature processing steps—which involve annealing the wafer at roughly 1,000 degrees Celsius—a temporary placeholder gate holds the structure in place. Once high-temperature processing is complete, the sacrificial silicon-germanium layers are selectively etched away, leaving the silicon ribbons hanging freely in open space. Next, an ultra-thin conformal layer of high-k insulating dielectric is deposited around every exposed ribbon to enhance electrostatic coupling, followed by the deposition of the final metal gate.

Though both FinFET (demonstrated in 1989) and Gate-All-Around (demonstrated in 1988) were conceived in research laboratories around the same time, their arrival in commercial high-volume manufacturing (HVM) occurred more than a decade apart. Intel introduced FinFET in 2011 at the 22nm node, whereas the first commercial GAA transistors were not shipped until Samsung deployed them in 2022. Asked why GAA took over three decades to reach production, Auth notes that having an architectural concept in the 1990s was only the beginning. The industry still had to invent, qualify, and sequence interim scaling solutions—such as strained silicon, high-k metal gate (HKMG), and FinFETs—before the massive tooling and material hurdles of GAA could be justified in high-volume production.

[10:17](https://www.youtube.com/watch?v=frYSOKvNiiE&t=617s) Transistor Scaling: From Dennard Scaling to the “Golden Age of Innovation”

Addressing why major architectural shifts take so long to introduce, an Intel engineering leader explains that foundries deliberately avoid taking on risky, complex challenges before they have to. As long as alternative levers can deliver the required performance gains, engineers pursue those first. Intel progressed along this incremental path by implementing strained silicon, high-κ metal gate (HKMG), and FinFETs before confronting the necessity of gate-all-around (GAA) architectures. GAA represents the ultimate transistor structure, but adopting it forces engineers to reinvent how to integrate past breakthroughs—such as high-κ metal gates—into the new geometry.

This level of innovation takes time because it frequently depends on materials that have never been used in semiconductor fabs and brand-new machinery that tool vendors must invent from scratch. Intel engineers must approach vendors specifying precise requirements: a machine capable of a novel deposition technique, a chemistry/gas capable of laying down a specific layer, or a specialized heating chuck with unique thermal characteristics. The R&D cycle is intensely iterative; teams produce test GAA transistors, discover failures, reassess their initial hypotheses, and test modified structures.

This stands in stark contrast to the R&D model of the 1980s and 1990s. In that era, the industry rode classical Dennard scaling and standard optical lithography. The recipe was predictable: scale dimensions downward, and transistors naturally became faster, more reliable, and more energy-efficient without changing the fundamental process flow. Once Dennard scaling broke down in the 2000s, simply shrinking features ceased to work. Reflecting on this turning point, the speaker notes:

> “Before, it was, ‘Try to not change anything.’ Now it’s, ‘Take the sledgehammer and start tearing the thing up and come up with some new idea.’”

Rather than lamenting the demise of Dennard scaling, he describes the subsequent period as an exciting golden age for a self-described "transistor junkie." The playbook opened up completely to structural inventions and exotic materials:

- The variety of materials deployed in advanced fabs today is roughly 10× higher than in the 1990s. - Modern fabrication relies on techniques like atomic layer deposition (ALD), which deposits films and controls surfaces literally atom by atom. - The cadence shifted from maintaining a fixed process flow to introducing major structural innovations at each node: strained silicon, HKMG, FinFETs, gate-all-around nanosheets, and backside power delivery.

```mermaid flowchart LR accTitle: Evolution of Transistor Scaling Paradigms accDescr: Shows the progression from Dennard scaling to the modern era of structural innovations and new materials.

subgraph Classical["1980s–1990s: Dennard Era"] A["Planar Transistors"] --> B["Shrink Dimensions"] B --> C["Same Process Flow"] end

subgraph Modern["2000s–Present: Structural Innovation"] D["Strained Silicon"] --> E["High-κ Metal Gate"] E --> F["FinFETs"] F --> G["Gate-All-Around & Backside Power"] end

C -->|"Dennard Scaling Breaks"| D ```

---

[13:13](https://www.youtube.com/watch?v=frYSOKvNiiE&t=793s) High-NA EUV: Why It Makes Sense for Intel but Not TSMC

For its upcoming 14A node, Intel is adopting High Numerical Aperture Extreme Ultraviolet (High-NA EUV) lithography. Both standard EUV and High-NA EUV utilize light at a 13.5 nm wavelength, but High-NA redesigns the optical train to project light through a larger lens opening. Numerical aperture measures how wide a cone of light the mirror optics can focus onto the wafer surface; a wider cone produces a smaller focused spot, allowing finer features to be printed. While standard EUV systems feature an NA of 0.33, High-NA systems increase the aperture to 0.55. This enables High-NA tools to print patterns roughly 1.7× smaller in a single exposure pass.

When transistor or wire dimensions shrink below a lithography tool's single-exposure resolution limit, chipmakers must resort to multi-patterning—splitting the design layout across two, three, or four separate masks and passes. Every additional pass consumes throughput on lithography equipment costing approximately $200 million per machine while compounding defect opportunities and edge-placement errors. Although High-NA machines cost roughly double an existing EUV tool (approaching $350–400 million), they eliminate the need for multi-patterning passes. The economic viability of High-NA boils down to whether the cycle time saved and defect reduction outweigh the machine's exorbitant capital cost.

TSMC has publicly taken the position that High-NA does not make economic sense for them in the near term, whereas Intel is adopting it on 14A. This divergence stems directly from their architectural choices around backside power delivery:

> “High-NA’s a good example of where, because of the architecture of our technology versus TSMC’s, we make different conclusions off of the same tool set.”

```mermaid flowchart TD accTitle: Comparison of Backside Power vs Standard Frontside Routing for High-NA Lithography accDescr: Illustrates how backside power relieves pitch requirements to allow single-pass High-NA printing.

subgraph IntelPath["Intel 14A Architecture"] direction TB A1["Power Lines Moved to Backside"] --> B1["Relieved Pitch on Frontside Signal Wires"] B1 --> C1["Direct Single-Pass High-NA EUV Printing"] C1 --> D1["Cost & Defect Reduction"] end

subgraph TSMCPath["Conventional Architecture"] direction TB A2["Signal & Thick Power Packed on Front"] --> B2["Extremely Tight Pitches Required"] B2 --> C2["Tighter Than Single High-NA Pass Pitch"] C2 --> D2["Must Use Multi-Patterning EUV; High-NA ROI Falls"] end ```

In a traditional chip, thick, low-resistance power distribution rails and thin signal interconnects must share the upper metallization stack above the silicon substrate. Because signal lines must be spaced carefully to prevent cross-talk and capacitive coupling, crowding both power and signal on the front creates an interconnect bottleneck. Intel’s architecture separates the two networks: power rails are routed underneath the active silicon from the back of the wafer, freeing up frontside routing space.

Because Intel uses backside power, frontside interconnect pitches do not need to be forced down to extreme dimensions, falling directly into the sweet spot that can be resolved in a single High-NA exposure. TSMC, relying on conventional frontside power delivery for earlier generations, must pack lines so tightly that even a single High-NA pass cannot resolve them without multi-patterning. For TSMC, adopting High-NA would still require double-patterning, invalidating the machine's economic justification. On 14A, Intel offers High-NA as an optional customer configuration, weighing specific project value against the added process complexity.

---

[16:13](https://www.youtube.com/watch?v=frYSOKvNiiE&t=973s) The Foundry Learning Curve: Developing Customer-Ready PDKs

Transitioning from an Integrated Device Manufacturer (IDM) that fabricates internal designs into a merchant foundry serving external customers requires Intel to undergo a steep learning curve. Historically, Intel’s design and manufacturing groups collaborated through close internal feedback; fab engineers shared raw transistor data with internal architecture teams without requiring a rigid, industry-standard Process Design Kit (PDK). A foundry, however, must provide external fabless clients with a comprehensive PDK—a formalized rulebook detailing design rules, device models, schematic-driven layout constraints, and design-for-manufacturability parameters.

Public reports surfaced regarding early delays and maturity issues with the PDK on the 18A node, where external customers found initial documentation and rule decks difficult to work with. Intel acknowledges that 18A originally began without the refined PDK infrastructure standard foundries offer. Foundry competitors took decades to mature their external interfacing, and Intel has had to rapidly incorporate customer feedback regarding rule completeness, verification accuracy, and release readiness.

Intel measures PDK development against standardized maturity benchmarks (progressing through PDK 0.5, PDK 0.9, to general production 1.0). The lessons learned from the 18A bring-up have been folded into 14A, which is architected to provide mature, high-quality PDKs from the start of customer engagement. Historically, internal-only manufacturing limited Intel to its own product volumes, whereas TSMC’s open foundry model granted it exposure to diverse customer workloads, vastly higher total wafer volumes, rapid operational learning cycles, and relentless schedule discipline.

---

[19:20](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1160s) The Tech Tree: Historical Inevitability vs. Radical Shifts

When asked whether semiconductor history could have diverged along an entirely different "tech tree"—perhaps bypassing gate-all-around entirely—the Intel leader reflects on the inevitability of specific physics-driven breakthroughs versus radical engineering bets. Transistor channel control follows fundamental electrostatic laws: as channel lengths scale down to the nanometer regime, the gate electrode must enclose the channel on more sides to maintain gate control and suppress sub-threshold leakage currents. The evolution from planar (1 side) to FinFET (3 sides) and ultimately to gate-all-around (4 sides) was an electrostatic imperative that researchers anticipated as far back as the 1990s.

In contrast, other modern techniques were far from obvious:

> “Backside power, that one’s pretty out there. Even in the ’90s, the idea that you’re going to strip off the entire silicon substrate and put lines on the backside, that one is probably something that’s a little bit out there.”

The realization of backside power requires grinding away almost the entire bulk silicon wafer down to a layer only tens of nanometers thick, flipping the wafer, bonding it to a carrier substrate, and constructing a multi-layer metallization grid on the reverse side with lithographic alignment through the wafer.

Regarding wiring materials, copper remains the dominant standard for bulk on-chip wiring due to its exceptional electrical conductivity and electromigration resistance. However, copper hits a physical limit at the lowest metallization layers: when wire dimensions become smaller than the mean free path of an electron in copper, electron scattering off sidewall barriers and grain boundaries causes resistance to skyrocket. Consequently, while copper will remain standard for upper, wider interconnect layers, Intel confirms that replacing copper with alternative metals (such as ruthenium) is becoming inevitable for the absolute tightest pitches.

[20:28](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1228s) 3D Stacking, CFET, and the Thermal Bottleneck

Transitioning to gate-all-around (GAA) architectures and backside power delivery fundamentally shifts the paradigm of chip construction. Historically, chips were built strictly from the bottom up on top of a single substrate. Under this new regime, a transistor essentially floats suspended inside the interconnect layers, prompting architects to question why they cannot simply alternate layers of transistors and wiring into fully integrated 3D monolithic structures, rather than just stacking discrete chips together. While 3D architectures are already mature in memory technologies like NAND and are actively being pursued for DRAM, logic presents a much steeper challenge. Industry roadmaps are often artificially constrained by short planning cycles of roughly four years, making speculative architectures for 2045 seem impossibly distant, even though incremental four-year leaps eventually make exotic structures achievable. As an Intel technologist points out regarding long-term visibility: “We limit ourselves by what we see as possible in the next four years.”

```mermaid flowchart TD accTitle: Transistor Evolution from Planar to 3D Stacking accDescr: Progression showing how planar side-by-side transistors evolve into GAA, CFET, and integrated 3D monolithic logic.

subgraph Planar["Traditional Architecture"] direction LR P1["Substrate Base"] --> P2["Side-by-Side N-type & P-type"] P2 --> P3["Standard Top Interconnect"] end

subgraph Modern["GAA & Backside Power"] direction LR G1["Backside Interconnect (Power)"] --> G2["Floating GAA Transistors"] G2 --> G3["Frontside Interconnect (Signal)"] end

subgraph Future["Monolithic 3D & CFET"] direction LR C1["Stacked CFET (N-over-P)"] --> C2["Alternating Interconnects"] C2 --> C3["Multi-layer 3D Logic"] end

Planar --> Modern --> Future ```

The immediate vertical leap begins with the transistors themselves through Complementary Field-Effect Transistors (CFET). Standard circuits require pairing complementary n-type and p-type transistors, which operate identically but with inverted electrical charges. Currently, chipmakers fabricate these pairs side by side. CFET stacks the n-type and p-type directly atop one another, doubling transistor density within the exact same footprint. However, building upward in logic introduces severe thermal penalties that memory stacks like High Bandwidth Memory (HBM) and 3D NAND do not experience to the same degree, because active logic consumes vastly more power.

Addressing whether heat dissipation represents the ultimate long-term ceiling for computing, Intel leadership notes that computing limits have always boiled down to three fundamental, interconnected pillars: switching frequency (how fast the device toggles), power efficiency (how much energy each switch consumes), and heat dissipation (how efficiently generated thermal energy is removed). While these three limiters have been debated in literature for over two decades, system-level simulation and analysis tools specifically tailored to 3D logic thermal dissipation remain in their infancy.

- CFET stacks n-type and p-type transistors vertically to achieve up to a 2x density increase over side-by-side placement. - Three fundamental physics limits govern compute scaling: device switching frequency, power efficiency per switch, and thermal dissipation. - Long-range process technology development typically maintains high visibility only for about a four-year horizon at any given time.

[23:45](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1425s) Inside Intel's "Hot Topics" Meeting and Risk Culture

Engineering resources, tool time, and physical test wafers are strictly finite, meaning the hundreds of micro-experiments required to bring up advanced process nodes like Intel 18A and 18A-P must be ruthlessly triaged. That prioritization happens inside Intel’s high-stakes "Hot Topics" meetings, led by senior integration figures like Kevin Fischer. In these sessions, process and integration engineers pitch experiments aimed at raising yields and boosting drive currents, while leadership decides which data is missing, which experiments proceed, and how to accelerate cycle times. Fischer emphasizes that bringing up a leading-edge node demands an aggressive operational pace, where waiting for absolute certainty is fatal: “One thing you learn in this industry is that you will never have a complete data set.”

Fischer acknowledges that his assertive posture in these meetings can make him seem demanding, but he views it as an indispensable driver of corporate urgency. Frontline research engineers often operate within narrow technical silos; when they encounter a cross-functional denial or an organizational roadblock, their instinct is often to stop and accept the barrier. Leadership must intervene to force calculated risks directly onto the factory floor, weighing technical unknowns against the immediate risk to production schedules and commercial revenue. As Kevin Fischer frames the urgency required to protect node delivery: “If you want to wait for a complete data set, you’ve waited too long. It’s already too late.”

[26:39](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1599s) Tackling Epi Nodules and the "Hot Box" Priority System

One concrete defect discussed in the Hot Topics meeting involves epitaxial growth, commonly referred to as "epi." In chip manufacturing, epitaxy involves flowing heated gases over a wafer surface so precursor atoms deposit precisely along the underlying crystalline lattice, using that base structure as an atomic template. Intel utilizes epitaxy to grow the raised source and drain crystals flanking the gate channel. During deposition, abnormal, hyper-accelerated crystalline growths—resembling microscopic tumors—can erupt on the wafer. These epi nodules bridge unintended gaps, causing direct shorts between adjacent source/drain regions and killing functional yield.

Resolving node-threatening defects like nodules requires running multiple parallel tracks: developing specialized post-growth cleaning flushes to strip the nodules away after they nucleate, while simultaneously troubleshooting the deposition chamber kinetics to eliminate the root contamination source. To accelerate these pivotal trials, the fab operates a tiered priority system known as "hot boxes." The most critical classification, HotBox 1, grants a wafer lot absolute right-of-way across every tool in the facility, clearing all standard queue times. Because halting normal production lots to clear tools for a single experiment significantly degrades overall factory efficiency and tool utilization, manufacturing managers treat HotBox 1 sparingly, comparing it to an open diamond carpool lane where all normal highway traffic is cleared aside so one car can race through unimpeded.

- Epitaxy (epi) uses gas-phase precursors to continue the underlying substrate's single-crystal lattice structure to form transistor source and drain terminals. - Epi nodules act as localized crystalline shorts between adjacent terminals, rendering the underlying transistor circuitry completely inoperable. - Intel factories use a graded "hot box" priority hierarchy; HotBox 1 lots bypass all tool queues but introduce throughput drag across the fab line. - Parallel defect mitigation requires pursuing curative cleans alongside upstream root-cause chamber fixes simultaneously.

*(Dwarkesh highlights sponsor Jane Street, noting how their engineers repurposed Intel's hardware-level Processor Trace feature—which records fine-grained instruction streams and function calls—to build an internal diagnostic tool called magic-trace for pinpointing microsecond-level network latency anomalies in live trading systems.)*

[29:31](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1771s) Replacing Copper with Ruthenium Interconnects

Beyond the active transistor level lies the interconnect stack: more than a dozen intricate layers of metal wiring responsible for routing signals and power across billions of transistors. For decades, copper has served as the industry-standard metal for these lines. However, as wire pitches drop down to extreme dimensions, copper exhibits steep increases in electrical resistance. In Intel’s research labs, Jack Kavalieros and research teams are actively investigating alternative conductive materials, focusing heavily on elemental ruthenium as a successor for tight-pitch wiring layers.

```mermaid flowchart LR accTitle: Copper vs. Ruthenium Interconnect Cross-Section accDescr: Comparison showing how copper requires a resistive liner that chokes scaled wires, whereas etchable ruthenium eliminates the liner entirely.

subgraph CopperWire["Scaled Copper Interconnect"] direction TB C_Liner["Resistive Diffusion Liner / Glue Layer"] C_Core["Constricted Copper Conductor Core"] C_Liner --- C_Core end

subgraph RutheniumWire["Scaled Ruthenium Interconnect"] direction TB R_Core["Full-Volume Ruthenium Conductor (Directly Etched / Liner-Free)"] end

CopperWire -.->|"Pitches below ~20nm"| RutheniumWire ```

While bulk ruthenium inherently possesses higher electrical resistivity than bulk copper, it behaves far better at extremely small geometries. Copper wiring cannot be laid down directly against dielectric insulating material; it requires a protective barrier or "liner"—an adhesive transition layer that prevents copper atoms from migrating into the adjacent insulator and ensures proper adhesion. At tightly scaled pitches, this resistive liner consumes an increasingly large fraction of the trench volume, leaving only a tiny conduit for actual copper conduction. Ruthenium, by contrast, can be directly patterned and etched cleanly without requiring a diffusion liner, maximizing the active cross-sectional conducting area. At pitch dimensions below roughly 20 nanometers (where approximately half the pitch is the metal line and half is the insulating dielectric), ruthenium crosses over to provide superior net conductivity compared to lined copper.

- Modern logic chips contain more than a dozen stacked metallization layers forming the interconnect network. - Conventional copper lines require resistive diffusion barrier liners to guarantee mechanical adhesion and prevent atomic drift. - Ruthenium can be subtractively etched without an adhesive liner, eliminating the volume penalty imposed by conventional barrier layers. - The resistivity crossover threshold where liner-free ruthenium outperforms lined copper occurs around a 20-nanometer interconnect pitch. - As Jack Kavalieros explains regarding the geometry trade-off: “Now you scale those very fine dimensions, and if you can trade off that resistive liner with no liner, ruthenium starts to win.”

[31:05](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1865s) The Materials Tradeoff: Copper, Cobalt, and Ruthenium

The interconnect stack consists of interlocking copper lines routed to form electrical pathways throughout the die. Historically, depositing copper has always required an underlying barrier or liner layer. At older process dimensions, that liner occupied a significant share of the total cross-sectional area, choking off the conduction path. However, as fabrication teams scaled and thinned down the liner over time, copper re-emerged as the strongest contender for the interconnect layers.

```mermaid flowchart LR accTitle: Evolution of Interconnect Metal Choices accDescr: Progression showing early copper with thick liners moving to cobalt, then back to copper with thin liners, and toward ruthenium.

subgraph Past["Past Nodes"] A["Copper + Thick Liner (Liner limits conduction)"] B["Cobalt (Selected for 10nm)"] end

subgraph Present["Current Nodes"] C["Copper + Thinned Liner (Regains dominance)"] end

subgraph Future["Future Nodes"] D["Ruthenium (Potential next-gen metal)"] end

A -->|"10nm transition"| B B -->|"Liner scaling"| C C -->|"Atomic limits"| D ```

When Dwarkesh Patel asks how engineers determine whether a material transition is ready for high-volume manufacturing—pointing out the difficulties Intel faced when moving from copper to cobalt at the 10nm node—the response highlights the friction between isolated material capability and holistic integration. Decisions must be made under strict delivery deadlines, evaluating vendor toolsets, scalability, and how materials interface with neighboring transistor structures. As the Intel engineer explains:

> “At the time we made a decision for cobalt, it was the forerunner. The results were stronger at the time. But as we work with our ecosystem externally, the vendor ecosystem that provides these materials and the tools that we integrate them with, we find solutions down the road that may bring copper back in line as being the stronger of the two.”

- Integrating replacement materials depends on tool readiness across the entire supplier ecosystem, not just standalone electrical performance in a test vehicle. - For each upcoming node, Intel continuously evaluates multiple metallization alternatives as the delivery deadline approaches. - While cobalt took precedence at 10nm, copper returned once liner technology improved, and ruthenium stands as the potential successor for future fine-pitch layers.

---

[32:41](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1961s) CFET and Vertical Scaling Challenges

Complementary FET (CFET) represents the eventual shift toward vertically stacking transistors on top of one another, pursued by Intel, its direct competitors, and academic research labs alike. Traditional planar scaling forced NMOS and PMOS devices into increasingly compressed side-by-side lateral footprints. CFET relaxes lateral footprint constraints by putting one device directly over the other, but it introduces a severe vertical wiring problem. Connections that previously ran laterally across the top or bottom surface must now plunge vertically between the stacked channels.

The primary manufacturing bottleneck centers on high-aspect-ratio processing. Etching deep, ultra-narrow vertical trenches between the devices pushes physical limits. Once etched, these deep cavities must be completely filled with metal and dielectric layers without leaving voids or trapped air pockets, which degrade structural and electrical integrity.

- CFET moves NMOS and PMOS from adjacent lateral positions to a stacked 3D arrangement. - Moving connections vertically dramatically increases the aspect ratio of required vias and trenches. - Filling these high-aspect-ratio voids without creating air gaps remains a major obstacle for fabrication tool vendors.

---

[34:06](https://www.youtube.com/watch?v=frYSOKvNiiE&t=2046s) Prototyping Architectures via Short-Loop Test Vehicles

Full high-volume semiconductor processes require thousands of individual processing steps and run for a month or longer per wafer. To avoid paralyzing turnaround times when developing complex architectures like CFET, Intel relies on "short-loop" test vehicles. These targeted test vehicles isolate specific unit cells—such as individual diodes, isolated capacitors, or simplified single-nanoribbon pairs—allowing engineers to rapidly gather chemical and electrical parameters before combining them into full-flow prototypes.

```mermaid flowchart TD accTitle: Short-Loop Development Flow for CFET accDescr: Step-by-step evolution from basic electrical components to full multi-ribbon CFET architectures.

subgraph UnitLevel["Unit Cell Evaluation"] U1["Isolated Components (Diodes, Capacitors)"] U2["Single-Ribbon Stack (1 NMOS wire over 1 PMOS wire)"] end

subgraph Integration["Vehicle Scaling"] I1["High-Aspect-Ratio Metallization"] I2["EUV / E-Beam Patterning Verification"] end

subgraph Target["Full High-Volume Manufacturing"] P1["Full CFET Stack (4 Ribbons over 4 Ribbons)"] end

U1 --> U2 U2 --> I1 I1 --> I2 I2 --> P1 ```

Rather than jumping directly to an eight-ribbon stack (such as four NMOS ribbons over four PMOS ribbons), early functional CFET prototypes use a single-wire architecture (one NMOS wire over one PMOS wire). This dramatically reduces the vertical aspect ratio while preserving the ability to evaluate vertical gate control, inter-device spacing, and cross-tier contact routing.

- Full wafer manufacturing runs require thousands of steps and over a month of processing time, making quick iteration impossible on standard production flows. - Short-loop vehicles validate unit operations, isolating whether a single layer, junction, or dielectric meets baseline specifications. - Current lab prototypes utilize EUV lithography and electron-beam (E-beam) patterning to test geometries that match the exact physical dimensions targeted for eventual high-volume production. - R&D lines are actively experimenting with 2D materials, such as transition metal dichalcogenides (TMDs), which form single-atom-thick monolayers for ultra-scaled channel conduction.

---

[36:43](https://www.youtube.com/watch?v=frYSOKvNiiE&t=2203s) The Decade-Long Path from Lab Prototype to High-Volume Production

Dwarkesh questions why, if working CFET devices with production-scale feature sizes already function inside Intel's development labs, it still takes approximately a decade for those innovations to reach consumer electronics. The Intel engineer contrasts the adoption of novel materials with that of novel 3D architectures. While materials present basic chemical compatibility hurdles, full architectural shifts compound geometric and manufacturing stress across every step of the fab.

A lab prototype with a single ribbon stacked over another ribbon proves physical feasibility, but it does not deliver an immediate commercial performance gain over mature side-by-side nanoribbon (gate-all-around) designs. Extracting superior performance requires scaling to multi-ribbon tiers, refining contact resistances, perfecting selective deposition, and ensuring that hundreds of downstream thermal and chemical steps do not degrade delicate underlying layers. As the engineer details:

> “There’s a thousand different steps that all have to come together in a very unique way to make the performance compatible or actually supersede the prior technology.”

When screening experimental candidates like 2D materials, failure often strikes at basic mechanical or thermal interfaces. An engineer can successfully deposit a single-atom monolayer and verify its electrical properties, only to discover that the subsequent metallization layer exhibits zero physical adhesion. In other cases, capping layers fail to form a true hermetic seal; subsequent chemical washes or reactive process gases seep past the cap, altering the material's internal lattice structure and forcing the team to scrap the concept.

- A proof-of-concept device operating in a laboratory does not automatically match the yield, reliability, or drive current of the mature generation it seeks to replace. - Simple material failures include poor surface adhesion, where overlying contacts physically peel off the active channel. - Gas permeability issues can ruin candidate materials when downstream processing gases penetrate non-hermetic barrier caps and destroy device stability.

---

[39:45](https://www.youtube.com/watch?v=frYSOKvNiiE&t=2385s) The Interconnect Bottleneck and the Rise of Hybrid Bonding

While stacking individual transistors vertically remains confined to advanced R&D, stacking entire silicon dies is already deployed in volume manufacturing to bypass data movement bottlenecks. Modern AI processors—such as Nvidia’s Blackwell platform, which combines two monolithic processor dies bordered by eight high-bandwidth memory (HBM) stacks—are governed primarily by data-transfer rates rather than raw compute cycles.

```mermaid flowchart TD accTitle: Evolution of Packaging Technologies accDescr: Transition from side-by-side planar chip wiring to 2.5D interposers and direct 3D hybrid bonding.

subgraph Standard["2D Packaging"] A["Side-by-side dies Perimeter edge wiring"] end

subgraph Interposer["2.5D Packaging"] B["Silicon Interposer High-density surface routing"] end

subgraph Direct3D["3D Hybrid Bonding"] C["Direct Cu-to-Cu & Oxide-to-Oxide Fusion Eliminates solder bumps entirely"] end

A -->|"Overcoming perimeter limits"| B B -->|"Eliminating bump resistance"| C ```

When two planar chips communicate along adjacent edges, doubling their dimensions quadruples their internal circuit area while merely doubling the available edge perimeter for I/O routing. This classic area-versus-perimeter scaling penalty forces data traffic to congest at the perimeter. The semiconductor industry addresses this by evolving through three distinct packaging eras:

Hybrid bonding eliminates traditional solder microbumps entirely. Because microbumps are physically bulky, introduce parasitic resistance, and demand minimum pitch clearances, they cap interconnect density. In hybrid bonding, copper pads and surrounding dielectric surfaces are polished atomically flat, carefully aligned, brought into contact, and heated. The copper expands thermally to form a seamless electrical connection while the dielectric fuses simultaneously, yielding a dramatic leap in interconnect density.

- In large-scale AI workloads, system throughput is predominantly throttled by chip-to-chip bandwidth rather than raw compute capabilities. - The area-versus-perimeter scaling bottleneck means computational capacity expands quadratically with chip size while edge-to-edge communication channels expand only linearly. - Hybrid bonding achieves unprecedented interconnect density by bypassing solder bumps, pushing copper pads into direct, seamless fusion alongside adjacent dielectric bonding layers.

[42:12](https://www.youtube.com/watch?v=frYSOKvNiiE&t=2532s) Sponsor Break: Antithesis and Eliminating Non-Determinism

Dwarkesh Patel opens by noting that in advanced packaging, it took significant time to overcome initial defect and alignment hurdles, leading into a discussion with Tyler Osborn, a Director in Intel’s Advanced Packaging Technology Development group. Before diving into the lab work, Patel steps back to address a fundamental computing problem. For over five decades, Intel has pushed x86 CPUs for raw execution speed. However, critical architectural tricks like caching, branch prediction, and speculative execution inevitably destroy determinism: an identical series of instructions might take 4 cycles in one run and 300 cycles in the next. When multiplied across billions of instructions running on concurrent threads and cores, these non-deterministic variances turn into elusive, hard-to-reproduce bugs.

To eliminate this class of failure, Antithesis built a fully deterministic computing environment. Their engineering team identified every single interface in Intel's x86 architecture where non-determinism could enter the system—ranging from network packets and disk reads down to clock cycles and temperature sensors—and either sealed those interfaces shut or swapped them with controlled simulations. On this bedrock, Antithesis runs a platform that can compress years of software hardening into minutes by branching software execution across thousands of parallel states, injecting faults, and systematically guiding execution paths toward one-in-a-billion edge cases. This setup allows software teams and autonomous agents to perfectly reproduce any anomaly, time travel through execution traces, and pinpoint root causes.

[43:53](https://www.youtube.com/watch?v=frYSOKvNiiE&t=2633s) Wafer-to-Wafer vs. Die-to-Wafer Hybrid Bonding

Turning back to packaging, Patel asks Osborn about the trade-offs between die-to-die and die-to-wafer hybrid bonding. Osborn clarifies Intel’s internal terminology: what is often called "die-to-die" externally is typically referred to as "wafer-to-wafer" inside Intel, where an entire processed wafer is bonded directly to another full wafer. While wafer-to-wafer stacking dominates the CMOS image sensor market and is being explored for memory stacking, it imposes severe geometric and yield constraints. Both dies must have an exact 1:1 dimensional match, and any mismatch in the spatial distribution of good versus bad dies across the two wafers destroys overall yield through random pairing of good dies with defective ones.

By contrast, the chip-to-wafer (die-to-wafer) methodology lets engineers test and singulate dies beforehand. As Tyler Osborn explains, “Whereas with chip to wafer, I can dictate the terms. I can singulate and have known good dies that I’ve tested at the chip level, and then only bond known good to a known good base position.” Osborn notes that Intel maintains active capabilities in both techniques, but for high-performance logic-to-logic architectures, chip-to-wafer remains the most practical and yield-efficient path forward.

```mermaid flowchart TD accTitle: Comparison of Wafer-to-Wafer and Chip-to-Wafer Packaging accDescr: Diagram illustrating the operational and yield differences between wafer-to-wafer bonding and chip-to-wafer bonding.

subgraph W2W["Wafer-to-Wafer Bonding"] W1["Top Wafer (Good & Bad Dies)"] W2["Bottom Wafer (Good & Bad Dies)"] W1 --- W2 W2 --> R1["Requires identical die footprints\nYield suffers from random bad-to-good pairings"] end

subgraph C2W["Chip-to-Wafer Bonding"] D1["Pre-tested Known Good Dies (KGD)"] W3["Base Wafer with Known Good Sites"] D1 -->|"Selective Placement"| W3 W3 --> R2["Flexible die sizing\nMaximizes final assembly yield"] end ```

[45:30](https://www.youtube.com/watch?v=frYSOKvNiiE&t=2730s) Pitch Scaling and Connecting Internal Silicon Layers

Discussing interconnect scaling, Osborn charts the historical trajectory of first-level packaging pitches. Fifteen years ago, interconnect pitches sat between 130 and 150 microns. Today, Intel’s Foveros technology operates in high-volume manufacturing (HVM) at a 25-micron pitch, while developmental hybrid bonding is pushing sub-10 microns. Looking further ahead, research presented at packaging conferences like the IEEE Electronic Components and Technology Conference (ECTC) has demonstrated reliable devices operating down to a 0.45-micron pitch—an entire order of magnitude denser than current high-volume manufacturing baselines.

This extreme pitch scaling fundamentally blurs the boundary between packaging and fab back-end interconnects. In the back end of the fab, the upper metal layers sit around 0.5 to 1.0 micron. If packaging interconnects can match or beat that 0.5-micron threshold, packaging engineers can effectively bypass top-level thick metals, stripping off upper layers to connect lower-level silicon wiring directly between stacked dies. Osborn highlights that this enables packaging to drastically cut down total IR drop (voltage droop) across transistor layers, while delivering enormous power savings—measured in picojoules per bit—for both high-bandwidth AI interfaces and client CPU-to-GPU interconnects.

- **15 Years Ago Interconnect:** 130–150 µm pitch. - **Current Foveros HVM:** 25 µm pitch. - **Current Hybrid Bonding Lab Targets:** Sub-10 µm pitch. - **Demonstrated Research (ECTC):** 0.45 µm pitch with proven reliability data. - **Back-End Fab Wiring Comparison:** 0.5–1.0 µm on the upper layers.

[48:00](https://www.youtube.com/watch?v=frYSOKvNiiE&t=2880s) Tool Bottlenecks and Node Fungibility with CTO Pushkar Ranade

Moving from packaging mechanics to industrial scale, Patel sits down with Pushkar Ranade, Intel’s Chief Technology Officer, to discuss the supply chain realities behind AI compute demand. Patel points out that ASML produces fewer than 100 EUV tools per year and has little capacity to exceed that figure before the end of the decade, forcing Intel, TSMC, and memory giants like SK Hynix to carve up a strictly limited machine pool. Ranade confirms that tool delivery limits output, but stresses that tool constraints extend far beyond ASML:

> “Even though there are multiple providers of other tools, once you lock into a process flow — let’s say 18A, which is a mature process now — we need a specific tool. We can’t just go and get a different tool for the same process. So we’re locked into that one tool, one supplier, and we rely on that.”

To mitigate this operational vulnerability across generational transitions, Intel designs process nodes for maximum tool fungibility. Transitioning from the mature 18A node to the upcoming 14A node (targeted around 2028), Intel aims to carry over roughly 80% of its existing fab toolset, reserving new equipment capital expenditures strictly for the unique tools required by denser lithographic geometries.

[50:05](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3005s) The Scaling Ceiling: Why Compute Output Cannot 10x Overnight

When asked what limits leading-edge wafer output even under hypothetical infinite CapEx budgets, Ranade explains that modern semiconductor processes are already operating near peak yield. Because existing lines are finely tuned, squeezing out incremental single-digit percentage yield improvements is exceptionally difficult. When Patel asks whether the global equipment supply chain could support a 10x expansion in leading-edge wafer output, Ranade gives a sobering assessment:

> “Not 10X, but probably 2X, yes.”

Patel notes the stark discrepancy between this manufacturing ceiling and the AI sector's trajectory of tripling compute demand year over year for a decade. Ranade insists that leading-edge wafer output cannot track those software growth curves unless every layer of the supply chain—from Tier-1 toolmakers down to raw component and sub-assembly suppliers—expands production capacity simultaneously.

Patel points out the asymmetric economic value created by the supply chain: a couple billion dollars of foundry CapEx can supply the advanced logic that drives upwards of $100 billion in recurring annual revenue for downstream AI model developers. Because downstream value is consolidating so rapidly among hyperscalers and AI labs, Ranade observes early shifts in commercial behavior. The semiconductor sector has moved from the vertically integrated models of thirty or forty years ago to a highly fragmented horizontal structure of foundries, equipment suppliers, and fabless designers. Now, hyperscalers and frontier AI labs have accumulated enough capital and demand that single entities could fully underwrite and consume the entire silicon output of multiple leading-edge fabs.

[53:01](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3181s) The Extreme Economics of Scale in Semiconductor Foundries

Dwarkesh Patel opens the discussion by noting that the semiconductor landscape has shifted from a fragmented ecosystem back toward a "pseudo-vertical" or "virtually vertically integrated" world. In this environment, TSMC is shipping upwards of three times as many leading-edge wafers as Intel. When Dwarkesh asks whether scale advantages begin to diminish past a certain point, Intel’s technical leadership explains that scale economics in semiconductor manufacturing are "probably the purest" across all advanced industries because of the staggering upfront capital requirements.

```mermaid flowchart TD accTitle: Fixed Cost Leverage in Leading-Edge Fabs accDescr: Diagram illustrating how high fixed costs translate tiny operational gains into massive revenue upside.

subgraph CostStructure["Fab Financial Reality"] FC["~80% Fixed Costs (Shells, Tools, Baseline Utilities)"] VC["~20% Variable Costs"] end

subgraph OperationalGains["Incremental Gains"] Util["Every +1% Fab Utilization"] Yield["Die Yield Lift (e.g., 60% to 65-70%)"] end

subgraph RevenueImpact["Output Leverage"] Rev["Massive Revenue Upside Per Unit Footprint"] end

FC --> Util Util --> Rev Yield --> Rev ```

Once a fab is constructed, approximately 80% of its total cost structure is entirely fixed. Consequently, every single additional percentage point of utilization or yield directly converts into outsized financial returns. The executive explains:

> “Once you build a fab, like 80% of your cost structure is fixed. What that means is every extra percentage of utilization is adding far more in revenue.”

Yield increases deliver non-linear advantages. Boosting die yield from 60% up to 65% or 70% produces drastically more sellable silicon from the exact same physical footprint without requiring more cleanroom space or additional tooling. These brutal economics explain the industry's massive consolidation over the past four decades: forty years ago, roughly 20 distinct foundries operated, but soaring fixed costs have thinned the herd down to just three leading-edge players today (TSMC, Intel, and Samsung).

---

[55:17](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3317s) Catching Up to TSMC: Technology Parity vs. Volume Scale

Addressing the overflow demand at TSMC—where the N3 node is heavily dominated by AI accelerators, primarily Nvidia, while general CPU demand also surges—Dwarkesh asks for Intel’s concrete plan to close the gap. The Intel executive clarifies that the catch-up challenge has two very distinct dimensions: technological capability and raw volume scale. Intel is already functionally equivalent in process technology, but expanding manufacturing capacity will be a multi-year, gradual process.

On the technology front, being off by a few percent in power, performance, or area (PPA) is largely irrelevant compared to predictability and execution:

> “You can be off by a few percent, but you need to be on time. Your execution needs to be such that your yields are very high to support very large and very rapid ramps. That actually is more important than catching up on a few percent in performance or area.”

Dwarkesh cites SemiAnalysis projections suggesting Intel’s upcoming 14A node (targeted for 2028) may only match the transistor density of TSMC’s N2 node. The executive disputes that specific benchmark, emphasizing that process nodes cannot be evaluated on a unidimensional axis: - **Transistor Varieties:** Foundries do not optimize for a single transistor type; they build specialized high-drive current transistors for raw performance alongside low-leakage variants for power efficiency. - **Embedded Memory:** Nodes integrate both high-density SRAM and high-performance SRAM arrays. - **Mixed-Signal Capabilities:** Nodes must seamlessly integrate analog circuitry and RF blocks to produce competitive, full-featured SoCs.

When Dwarkesh points out the stark contrast in annual capital expenditure—TSMC spending approximately $50 billion compared to Intel's roughly $20 billion—the executive counters that the comparison is somewhat skewed today. TSMC builds capacity for the entire global semiconductor market, whereas Intel has historically manufactured primarily for its own internal product lines. As Intel ramps its external foundry business, its CapEx is poised to grow accordingly.

---

[59:11](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3551s) The Memory Crunch and Hard Timelines for Fab Expansions

The conversation turns to Intel's strategic history, starting with its founding as a DRAM producer in the late 1960s and its decision to sell off its NAND flash business. With memory now standing as a multi-trillion-dollar bottleneck for AI scaling, the executive reflects candidly on that strategic divestiture:

> “Clearly, in hindsight, probably not the smartest time to sell off a flash memory business. There were good reasons why we did that when we did. Clearly, nobody could see this enormous demand.”

The executive highlights that the current AI supply crunch is actually far more severe for memory than it is for compute:

> “I would argue that the supply crunch is larger for memory today than it is for compute.”

Dwarkesh summarizes the industry's manufacturing timeline: marginal wafer production can be bumped up rapidly in the short term (within 12 months) by optimizing utilization, but total industry supply by 2030 is fundamentally capped. The Intel executive agrees. Reaching mid-2026, the industry faces severe lead-time constraints: - Placing an order for complex wafer fabrication equipment today carries roughly an 18-month lead time, pushing delivery into 2028. - Constructing new cleanroom shells and qualifying tools requires an additional several years, making substantial unexpected supply additions before 2030 practically impossible without an unprecedented acceleration across the entire global supply chain.

---

[01:01:02](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3662s) Elon Musk’s "Terafab" and Questioning Cleanroom Dogma

Dwarkesh asks about Intel's collaboration with Elon Musk on his ambitious "Terafab" concept. Musk concluded that his ventures (such as xAI and Tesla) will require such an immense volume of compute and memory that building an in-house fab was the only way to secure supply:

> “He came to the conclusion that his own businesses are going to require a lot of silicon. He thought maybe he should just do it all on his own. But unlike building a car, for example, this is such an intricate and complicated process that we thought we could work together to help accelerate his bringing up his fab.”

Dwarkesh observes that because upstream tooling supply is the true bottleneck, a new market entrant does not actually increase the net amount of leading-edge silicon globally; it simply guarantees allocation to that specific player. The executive acknowledges that while tools remain the hardest constraint, foundries also require immense supplies of power, water, consumables, and raw cleanroom floor space.

```mermaid flowchart LR accTitle: Semiconductor Industry Cost Escalation accDescr: Diagram tracing the exponential cost growth of fabs and High-NA EUV lithography tools.

subgraph HistoricalTrend["Cost Doubling Curve"] FabCost["Total Fab Shell & Fit-Out Doubling every 4-5 years"] LithoCost["Lithography Module Cost Doubling at >4-5 year pace"] end

subgraph ModernTooling["Current High-NA Reality"] Scanner["High-NA EUV Scanner Suite ~$400 Million Per System"] FutureRisk["Projected Extrapolation: $800M+ per tool set?"] end

FabCost --> ModernTooling LithoCost --> Scanner Scanner -.-> FutureRisk ```

The underlying capital intensity of fab construction is becoming unsustainable: - The total cost to construct an advanced fab has doubled every four to five years over several decades. - The patterning module—lithography—is escalating even faster. A single High-NA EUV scanner and its associated support equipment now costs roughly $400 million. - Simply extrapolating that trend suggests patterning suites could reach $800 million in the near future, which the executive notes "doesn’t really make sense."

This exponential cost curve forces a fundamental rethink of fab design. Because semiconductor manufacturing is so capital-intensive, the industry has become deeply risk-averse, treating decades-old operational flows as inviolable dogma. Incoming engineers are handed legacy recipes and "just take that as gospel."

The transistor roadmap from planar to FinFETs to gate-all-around (and eventually complementary FETs) is clear, but fab infrastructure itself remains largely unexamined. The executive challenges the most foundational assumptions of chipmaking:

> “Do you really need a clean room today? Do you need the infrastructure to be as sophisticated, as complex as it is today? Surely one can run an experiment where you have people eating hamburgers and smoking cigars in the research fab and see what happens to yield. That would be a great experiment to run, but no incumbent — Intel or TSMC or Samsung — would want to willingly do that.”

[01:06:26](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3986s) Risk Aversion and Rethinking Chip Design from a Clean Slate

The semiconductor manufacturing business operates under immense risk aversion, driven by the astronomical cost of any disruption. Because every single day lost in fab productivity carries an immense financial penalty, fab operators face intense fear of the unknown and resist fundamental architectural overhauls, even when radical redesigns—such as eliminating massive cleanrooms in the future—promise huge long-term savings. As the Intel speaker explains: “Nobody is going to willingly take that risk. That’s why I think sometimes it’s good to just start with a clean slate and rethink everything.”

This dynamic extends directly into chip architecture as well. Many foundational practices in modern CPU design were locked into place thirty years ago, and while sticking to three-decade-old methodologies may no longer be optimal, replacing them is extraordinarily complex. While chip designers enjoy somewhat higher latitude to take risks than fab operators running multi-billion-dollar cleanrooms, the underlying economics have reached an inflection point where continuing business as usual is no longer viable, making clean-slate rethinking a necessary pursuit.

- **Downtime Penalties:** A single lost day of fab throughput costs an astronomical, unrecoverable sum of money, making fab managers fundamentally cautious about adopting unproven facility paradigms. - **Legacy Architecture:** Core CPU design paradigms have remained largely rooted in decisions made 30 years ago due to the sheer complexity of redesigning processor flows from the ground up.

---

[01:07:36](https://www.youtube.com/watch?v=frYSOKvNiiE&t=4056s) Securing Upstream Tool Supply to Meet the AI Demand Surge

Dwarkesh Patel brings the discussion full circle to the central dilemma raised at the start of the tour: how Intel plans to cope with the explosive, incoming wave of AI compute demand. Given that Intel already owns the physical fab footprints and has room to expand them, the true structural ceiling will be the availability of leading-edge tools from upstream equipment makers like ASML. Dwarkesh suggests that Intel should aggressively raise as much capital as possible to place massive advance tool orders—mirroring the strategy Nvidia used to secure memory and key components through hundreds of billions of dollars in purchase commitments. Without lock-in commitments, the United States risks finding itself in a position where demand surges into trillions of dollars, but the physical tools required to produce the wafers reside primarily in Taiwan.

The Intel technical leader acknowledges the validity of this supply-chain lock-in strategy, admitting that the velocity of AI demand outpaced prior assumptions. Looking back at past capacity plans, the leader notes: “Had we known what we know today, we would have invested more like a year ago. Knowing what we know now, I think we’ll be investing more.”

```mermaid flowchart TD accTitle: Foundry Expansion Bottlenecks accDescr: A flow diagram showing how foundry scale is constrained by upstream tooling lead times rather than fab shell footprint.

subgraph Demand["Surging AI Demand"] A["Exponential Compute Demand"] end

subgraph Upstream["Upstream Supply Constraints"] B["Lithography & Tool Vendors (e.g., ASML High-NA EUV)"] C["Advance Capital Commitments & Orders"] end

subgraph Manufacturing["Foundry Execution"] D["Intel Fab Shell Capacity"] E["Global Leading-Edge Wafer Output"] end

A -->|"Drives need for"| C C -->|"Secures allocation from"| B B -->|"Delivers tools into"| D D -->|"Determines ultimate"| E ```

- **Tooling as the Hard Bottleneck:** Intel's physical expansion limit is not cleanroom square footage or fab shells, but the finite global manufacturing capacity of lithography and semiconductor equipment suppliers. - **The Nvidia Precedent:** Nvidia pre-emptively committed tens to hundreds of billions of dollars across its supply chain to guarantee advanced packaging and high-bandwidth memory (HBM) supply, serving as a template for foundries securing upstream tool production. - **Shifting Investment Cadence:** Intel acknowledges that having perfect foresight 12 months earlier would have prompted far larger capital outlays, and current planning reflects an escalated pace of investment to meet AI-driven wafer demand.

## Notable quotes > [23:45](https://www.youtube.com/watch?v=frYSOKvNiiE&t=1425s) If you want to wait for a complete data set, you’ve waited too long. It’s already too late. — Kevin Fischer

> [00:47](https://www.youtube.com/watch?v=frYSOKvNiiE&t=47s) What we’ve learned is that you don’t want to do too much innovation in one node, because the more innovation that you do, the more complex it becomes. — Chris Auth

> [55:17](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3317s) Your execution needs to be such that your yields are very high to support very large and very rapid ramps. That actually is more important than catching up on a few percent in performance or area.

> [53:01](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3181s) Once you build a fab, like 80% of your cost structure is fixed. What that means is every extra percentage of utilization is adding far more in revenue.

> [59:11](https://www.youtube.com/watch?v=frYSOKvNiiE&t=3551s) I would argue that the supply crunch is larger for memory today than it is for compute.

## Mentioned 14A, 18A, 18A-P, Antithesis, ASML, CFET, Chris Auth, Dwarkesh Patel, Elon Musk, Foveros, HBM, High-NA EUV, IEEE Electronic Components and Technology Conference (ECTC), Intel, Jack Kavalieros, Jane Street, Kevin Fischer, N2, N3, Nvidia, Nvidia Blackwell, Pushkar Ranade, Samsung, SemiAnalysis, SK Hynix, Tesla, TSMC, Tyler Osborn, WorkOS, xAI

## Video description I spent two days touring Intel’s most advanced fab and talking to its technical leadership to understand what the chips of the future will look like.

A lot of what's coming next – gate-all-around transistors, backside power, CFET, hybrid bonding – is hard to follow without actually seeing it, so we made all the awesome animated explainers that I wish I had while I was prepping.

I also asked Intel’s leadership how the semiconductor industry will cope with the enormous shock in demand from AI.

AI compute has grown 3x a year for the last decade, but according to Intel's CTO, Intel could only double leading-edge wafer production with today’s global stock of chipmaking tools.

What kinds of tricks can foundries pull to extend this crossover point where demand surges way ahead of supply?

This was a totally new format for us - hope you enjoy!

I also made flashcards for the concepts I had to learn to prep for this episode – link below.

𝐄𝐏𝐈𝐒𝐎𝐃𝐄 𝐋𝐈𝐍𝐊𝐒

* Flashcards: http://flashcards.dwarkesh.com/intel * Transcript: https://www.dwarkesh.com/p/intel-tour * Apple Podcasts: https://podcasts.apple.com/us/podcast/what-will-computer-chips-look-like-in-2045/id1516093381?i=1000797633702 * Spotify: https://open.spotify.com/episode/1kycOQ4f8ZHsXMOvUujdq6?si=NVKBI5NCRqirns5WPXzepQ

Music for this episode composed by Tom Fox @tomfoxcatalog

𝐒𝐏𝐎𝐍𝐒𝐎𝐑𝐒

* WorkOS helps you do business with enterprises. It gives you access to all the features most commonly required by enterprises: SSO, SCIM, RBAC, audit logs, and more. It’s easy to plug these features in — it only takes a few lines of code — and WorkOS is releasing new functionality all the time, including things like auth for agents. If you want to join the 3,000+ companies that rely on WorkOS, go to https://workos.com

* Jane Street built a powerful tool called magic-trace to help analyze and debug their trading systems. It only exists because one engineer noticed a feature on Intel chips called Processor Trace and thought it’d be valuable to build on top of. Now, traders and developers across Jane Street use magic-trace every single day! If you want to be trusted to pursue the ideas you think matter most, Jane Street is hiring. Go to https://janestreet.com/dwarkesh

* Antithesis’ testing platform lets you perfectly reproduce every single bug you find. That’s because it runs on a fully deterministic computer, which strips out all the unpredictability that can make certain bugs flaky and hard to pin down. To build it, Antithesis found every source of non-determinism in Intel’s x86 architecture and either sealed it off or replaced it with a controlled simulation. Learn more at https://antithesis.com/dwarkesh

To sponsor a future episode, visit https://dwarkesh.com/advertise.

𝐓𝐈𝐌𝐄𝐒𝐓𝐀𝐌𝐏𝐒 00:00:00 – Intro 00:00:47 – How Intel brings up a new process node 00:03:22 – What Intel learned from 10nm 00:06:28 – From planar transistors to gate-all-around 00:13:13 – Why High-NA EUV pays off for Intel but not TSMC 00:19:20 – Could chips have evolved completely differently? 00:23:33 – Inside Intel's "Hot Topics" meeting 00:29:30 – Replacing copper wires with ruthenium 00:32:41 – Why stacked transistors take a decade to ship 00:39:45 – Hybrid bonding and the chip-to-chip bottleneck 00:48:00 – There aren't enough tools to 10x chip production 00:53:14 – Can Intel catch up to TSMC? 01:01:02 – Terafab, and rethinking the fab from scratch

[Source](https://www.youtube.com/watch?v=frYSOKvNiiE)

中文简报

英特尔称设备瓶颈限制芯片扩产，难以应对AI需求激增全球芯片制造设备瓶颈使得代工厂尖端晶圆产能仅能翻倍，而AI需求正以每年三倍的速度增长。本期节目深入探讨了半导体行业迈向2045年之际，尖端芯片制造面临的技术与经济现实。Dwarkesh Patel参观了英特尔晶圆厂并采访了核心工程高管，以剖析关键架构转变，包括向RibbonFET、背面供电、钌互连以及CFET单片3D微缩的过渡。讨论重点总结了以往执行延误带来的教训，对比了英特尔采用高数值孔径EUV（High-NA EUV）与台积电的技术路线图，并审视了芯片-晶圆混合键合等先进封装创新。至关重要的是，英特尔领导层谈到了AI算力需求驱动下的结构性供应紧缺，指出尽管来自ASML等制造商的现有设备供应链或可支持尖端晶圆产出翻倍，但受制于设备交期和高昂资本成本，产能出现十倍扩张在物理层面上仍受到限制。英特尔高管评估认为，全球半导体设备供应链可支持尖端晶圆产出翻倍，但无法支持十倍的扩张以匹配每年约三倍增长的AI算力需求。 (50:05) 单台造价达3.5亿至4亿美元的高数值孔径EUV光刻机在英特尔14A制程上具有经济可行性，因为背面供电技术将正面布线间距放宽至单次曝光范围，而台积电则仍需进行双重图案化。 (13:13) 英特尔正在开发无衬层钌互连技术，以在约20纳米以下的间距中替代铜，从而避免极薄沟槽中扩散阻挡层引发的严重电阻增大和电子散射问题。 (29:30) 封装互连间距在Foveros量产中已从130–150微米降至25微米，且10微米以下的混合键合正直接与晶圆厂后端布线融合，从而绕过上层金属层。 (45:30)

Reading summary

During a tour of Intel's fabrication facilities, Intel technical leadership and Dwarkesh Patel discussed how surging AI demand is running into hard physical and industrial bottlenecks, forcing the semiconductor industry to pivot from traditional planar scaling to exotic 3D architectures, backside power delivery, and advanced packaging. Upstream Tooling and the Industrial Scaling Ceiling (48:00) Customer demand for leading-edge silicon currently runs 40% to 50% above maximum fabrication capacity, driven by AI compute requirements roughly tripling year over year. However, wafer output cannot simply scale 10x overnight to match downstream demand. Intel CTO Pushkar Ranade assesses that the global equipment supply chain could realistically support a 2x expansion, but not a 10x surge, because foundries are constrained by specialized fabrication tool availability and vendor lead times. Advanced equipment like ASML's EUV lithography systems—produced at fewer than 100 units annually—faces delivery lead times of around 18 months, meaning significant unplanned fab capacity additions cannot materialize before roughly 2030. Process Complexity, Risk Discipline, and EUV Economics (0:47) Developing a leading-edge node such as Intel 14A requires optimizing roughly 2,000 distinct cleanroom steps across several years of pathfinding. Intel's conservative operational discipline stems from its costly 10nm node delay, where attempting 'hyperscaling' via multi-patterning on older DUV tools rather than adopting EUV lithography cost the company its manufacturing lead to TSMC. For 14A, Intel is adopting High-NA EUV lithography, which increases the numerical aperture from 0.33 to 0.55 to print features 1.7× smaller in a single pass. While High-NA scanners approach $350–400 million each and TSMC has deemed them economically unviable in the near term, Intel argues that pairing High-NA with backside power delivery eliminates expensive multi-patterning passes and justifies the capital expense. Architectural Shifts: GAA, Backside Power, and CFET (6:28) Following the historical collapse of Dennard scaling, geometric shrinks alone no longer yield automatic performance and efficiency gains. To suppress parasitic sub-threshold leakage, transistor designs progressed from planar to 3D FinFETs and are now transitioning to Gate-All-Around (GAA) nanosheets, which wrap the gate around all four sides of the channel. Intel is pairing this with backside power delivery—stripping away bulk silicon to place power delivery networks on the reverse side of the wafer—to free frontside routing for signal lines. Further scaling points toward Complementary FET (CFET), stacking n-type and p-type transistors vertically. However, CFET requires solving extreme high-aspect-ratio etching and void-free metal fills, keeping production-scale CFET deployments years away despite working single-ribbon laboratory test vehicles. Interconnect Materials and Packaging as the New Frontier (29:31) As feature dimensions scale below 20 nanometers, conventional copper interconnects face steep resistance penalties because resistive diffusion liners consume a growing fraction of the wire trench. Intel is researching elemental ruthenium, which can be etched directly without a liner to preserve cross-sectional conducting area. Simultaneously, physical limits in monolithic silicon are shifting performance gains toward advanced packaging. While 2D planar chips face perimeter I/O bottlenecks, 3D hybrid bonding eliminates solder microbumps entirely, fusing copper contacts directly. Intel's Foveros technology currently operates at a 25-micron pitch in high-volume production, but packaging research has demonstrated connections down to a 0.45-micron pitch, effectively merging packaging with back-end silicon wiring to slash voltage drop and interconnect power. Foundry Economics and Customer Transition (53:01) Transitioning from an internal device manufacturer to an open foundry requires Intel to master commercial Process Design Kits (PDKs) and close the volume gap with TSMC, which currently ships upwards of three times more leading-edge wafers. Modern foundries operate under brutal scale economics where roughly 80% of fab cost structures are fixed, meaning slight percentage-point gains in tool utilization and yield translate into outsized financial margins. Intel leadership argues that closing the gap with TSMC hinges less on marginal differences in power, performance, and area than on absolute predictability, high yields, and disciplined execution schedules. While the physical roadmaps through 2045 point toward monolithic 3D logic and atomic-scale materials, the near-term velocity of computing remains strictly bound by supply chains: fab shells require billions of dollars and years to build, specialized lithography tools cannot scale output instantly, and memory shortages currently constrain AI systems even more tightly than raw compute.

精炼阅读摘要

英特尔技术领导层在与 Dwarkesh Patel 的交流中指出，AI 带来的算力需求激增正遭遇半导体物理微缩放缓与上游专用制造设备的硬性产能瓶颈。为突破限制，芯片制造正从传统的二维几何微缩全面转向环绕栅极（GAA）、背面供电、3D 垂直堆叠与先进封装，但制造端的高昂固定成本与漫长的供应链扩产周期仍制约着全球前沿晶圆的实际供给增速。先进制程研发的复杂性与10纳米教训 (0:47) 开发如 Intel 14A 等前沿制程通常需要超过三年的前瞻探索，单个晶圆在洁净室中需经历约 2,000 道独立工序。英特尔副总裁 Chris Auth 指出，现代良率管理依托在线自动量测与失效分析团队的透射电子显微镜（TEM）切片，精确定位缺陷在两千道工序中的具体站点。为避免过度创新引发失控，英特尔设立了严谨的“阶段门禁”（phase gate）机制，这源于其 10 纳米制程的惨痛教训。当年英特尔推行被称为“超微缩”（hyperscaling）的激进指标，在极紫外光刻（EUV）未就绪时强推多重曝光，导致量产延误近四年，不仅股价单日重挫超 15%，更将先发优势拱手让予台积电（TSMC）。晶体管演进与微缩路线的分歧抉择 (6:28) 随着器件尺度缩小引发短沟道效应和严重漏电，晶体管结构从平面走向三面包裹的 FinFET，并最终走向四面包裹的环绕栅极（GAA / RibbonFET），这一演进遵循了不可逆的静电学物理规律。然而在互连布线与光刻路线上，厂商策略出现分歧。在布线层微缩导致铜线因侧壁散射而阻抗飙升时，英特尔探索以无须扩散阻挡层的钌（Ruthenium）替代 20 纳米间距以下的底层铜互连。在光刻方面，Intel 14A 率先引入单价近 4 亿美元的 High-NA EUV（数值孔径 0.55），通过单次曝光消除昂贵的多重曝光步骤；而台积电鉴于自身技术架构短期内认为其经济效益不足。此外，英特尔将电源线移至晶圆背面的“背面供电”技术，需磨薄整片衬底晶圆并进行背部对准布线，虽属激进举措，却显著缓解了前沿光刻的布线压力。垂直堆叠构架与先进封装的崛起 (20:28) 受制于横向面积与热学限制，互连与堆叠技术向三维空间加速迁移。互补场效应晶体管（CFET）通过垂直叠放 NMOS 与 PMOS 突破侧向空间瓶颈，但其极高深宽比的垂直沟槽刻蚀与填充对制造设备提出了苛刻挑战。英特尔目前借助“短流程”（short-loop）单线对测试载具在实验室验证工艺可行性，但将其拓展至量产多纳米带结构通常需要近十年的时间周期。在芯片级互联上，为打破平面芯片“周长与面积”不成比例导致的 I/O 拥堵，封装技术正从 2.5D 中介层跃迁至 3D 混合键合（Direct Cu-to-Cu Hybrid Bonding）。英特尔先进封装主管 Tyler Osborn 指出，目前 Foveros 量产间距为 25 微米，实验室混合键合正迈向亚 10 微米，学术界展示的 0.45 微米间距甚至超越了晶圆厂顶层金属布线，不仅能实现已知良好芯片（KGD）的高良率键合，还能大幅削减压降（IR drop）并显著降低每比特能耗。晶圆制造的规模经济与代工业务转型 (48:00) 晶圆厂的财务现实表现为极度纯粹的规模经济：一座先进制程晶圆厂建成后，约 80% 的成本属于固定成本，微小的产能利用率提升或良率从 60% 增至 70% 都会非线性地转化为巨额收益回报。这也是历史上几十家代工厂整合至如今少数巨头的原因。在这一生态下，出货量达到英特尔三倍以上的台积电形成了巨大的规模壁垒。英特尔首席技术官 Pushkar Ranade 强调，制程竞争的关键在于交付的确定性与按时达产，而非微小的 PPA 指标差异。同时，从以往内部协同的 IDM 模式转向对外代工，英特尔必须补齐工艺设计套件（PDK）的成熟度短板，吸取 18A 早期规则库未达外部标准的教训，力争在 14A 阶段提供完全符合业界标准的 1.0 版本成熟 PDK。产能扩建周期的硬性上限与供应链约束 (50:05) 针对 AI 算力每年增长数倍的预期，英特尔管理层给出了冷静的产业判断：全球领先晶圆制造绝不可能实现短期内 10 倍的产能扩张，即便资金无限，短期也仅能实现约 2 倍增长。核心瓶颈在于专用设备供应链：ASML 每年交付的 EUV 光刻机不足百台，且高度定制的工艺流程一旦敲定便无法随意更换机台供应商；前沿设备订购到交付通常需约 18 个月，加之洁净室施工与机台校准，2030 年前的全球先进制程总产能基本已被刚性锁死。此外，高管坦言当前 AI 供应链中存储芯片（Memory）的缺口甚至比逻辑算力更为严峻，英特尔昔日剥离闪存业务在当下来看错失了庞大需求。面对动辄耗资数百亿美元的建厂成本与飙升的光刻机价格，下游云厂商与头部 AI 实验室已积累出足以包揽整座晶圆厂产出的资金实力，倒逼先进制程投资采取提前预订与高额资本绑定的策略。该对话表明，虽然向 GAA、CFET 和 3D 封装演进在物理理论与实验室原型上均已打通，但将其转化为可盈利的商业量产受制于严苛的物理良率、高昂的设备资本支出以及上游供应商有限的交付能力。在先进制程固定成本指数级膨胀的背景下，芯片制造业能否跟上下游 AI 爆发式的算力需求，依然取决于全产业链设备产能的协同突破与巨额资本下注的时机。

Source quotes

[23:45] Kevin Fischer: If you want to wait for a complete data set, you’ve waited too long. It’s already too late. [0:47] Chris Auth: What we’ve learned is that you don’t want to do too much innovation in one node, because the more innovation that you do, the more complex it becomes. [55:17] Your execution needs to be such that your yields are very high to support very large and very rapid ramps. That actually is more important than catching up on a few percent in performance or area. [53:01] Once you build a fab, like 80% of your cost structure is fixed. What that means is every extra percentage of utilization is adding far more in revenue. [59:11] I would argue that the supply crunch is larger for memory today than it is for compute.

Original transcript

[0:00] There’s never been as big a shock to the semiconductor industry [0:03] as the current surge in demand from AI. AI is driving incredible computing demand. [0:09] Easily 40-50% above our maximum capacity, which I’ve never seen before. [0:13] Progress in AI has been driven by exponentially increasing compute. [0:17] To sustain that progress, foundries like Intel will need to manufacture far more [0:21] leading-edge compute, both by producing more chips and by improving what each chip can do. [0:26] But the production of these chips is bottlenecked by tools that Intel buys from their suppliers. [0:31] Most famously, ASML’s EUV machines. If they don’t have the equipment, [0:34] they can’t make the chips here. I spent two days touring Intel’s fabs to [0:38] prepare for these interviews with its leadership. I wanted to understand what it takes to [0:42] manufacture the world’s most advanced chips and how hardware is shaping the future of AI. [0:47] I’m joined by Chris Auth, who leads development of all the processes [0:51] that are currently under manufacturing. The thing I want to understand in more [0:54] concrete detail is how the development of a new process actually happens. [1:00] If 14A is going to come out in three years or two years from now, [1:03] what is happening from now till then? I want you to walk me through as much [1:07] detail as you can, everything from the level of “how is the yield improving?” to what [1:12] kind of telemetry you guys look at? What kind of experiments do you guys run? [1:15] I want to understand what is going to happen over the next two years as concretely as possible. [1:22] 14A has been in development for about three-plus years at this stage, [1:28] so quite a bit of pre-work has been done to get it to the stage that it’s at right now. [1:32] Right now, we’re getting very close to where we’re finalizing the process. [1:35] We’re finalizing the tool sets that it will be manufactured on, [1:38] and we’re working on the fine-tuning of each of the process steps. [1:42] There are about 2,000 steps in the factory that you have to go do. [1:46] You need to do really intricate work at each one of those to make sure it’s fine-tuned, [1:51] it can go into manufacturing, it can run thousands of wafers a week on this process, [1:55] and it can be repeatable every single time. Right now, you might have a certain yield. [2:00] Walk me through how that increases month over month. [2:03] There’s a line running at 14A. What happens from now till next [2:07] month that will result in the yield changing? How do you identify where the defects are? [2:10] How do you fix that? There’s a constant [2:13] process that we go through in identifying defects. There are two main ways that we’ll identify them. [2:18] One is we have inline metrology. We have tools that will look at [2:22] the wafers and say, “Ah, there’s a defect there, there’s a defect there, there’s a defect there.” [2:26] Then also at the end of line, either electrical test or we sort and see where the fails are. [2:32] We will identify failures, and then we will get analysis on those failures. [2:36] We’ll cross-section it. You were in the TEM lab yesterday, [2:40] and you saw how you can get cross-sections. You’ll get a cross-section of a defect, [2:43] and from that, you’ll be able to say, “Oh, that defect is between these layers, so it [2:47] must have come from this section of the flow. Oh, we have inline metrology in that section, [2:53] which has identified defects. Those are the defects we need to go after.” [2:57] What we’ve learned is that you don’t want to do too much innovation in one node, [3:02] because the more innovation that you do, the more complex it becomes. [3:05] While you’ll be able to get that to work, you need to hit a certain schedule, and that’s the [3:10] schedule that your customer ultimately wants. Having that predictable schedule is a key piece. [3:14] You’ve got to figure out how much innovation you can put in in order to meet the customer’s [3:20] requirements in the timeline that they need it. Intel learned how costly that tradeoff can [3:24] be with delays to its 10 nanometer node, whose original target launch date was 2016, [3:28] but which didn’t begin manufacturing until 2018. Usually Intel has been the keeper of Moore’s Law, [3:34] a new cadence of manufacturing every two years, but their last [3:38] set of products slipped almost four years. Intel today having its worst day in four months, [3:44] the stock now down more than 15%. I also want to point out Taiwan [3:49] Semiconductor up 13% off of Intel’s bad news. Walk me through what lessons you think Intel [3:57] has learned from 10 nanometer. Ten nanometer was a good example [4:01] of where we had very aggressive targets. We were doing what was called hyperscaling [4:06] at the time, so we were scaling much faster than what had been historically done. [4:10] In order to do that, we came up with all sorts of innovative ideas on how we could achieve that [4:18] without new tools, because the tools weren’t ready. [4:23] That put a lot of burden on the process and a lot of burden on the engineers. [4:27] Now, at the end of the day, 10 nanometer is a great technology. [4:30] It has world-class yield, it has world-class performance, it has world-class cost, [4:34] but it took us longer to do that than what we would have liked. [4:38] So we’ve tried to take that learning into future technology nodes and say, “Hey, we [4:43] need to limit the amount of innovation we put in there to make sure that we keep it on schedule.” [4:46] What do you think was the main technology that should’ve been saved for a future version? [4:52] EUV was probably the big thing. When we started to define 10 nanometer, [4:56] the conclusion was EUV was not ready. EUV is extreme ultraviolet lithography. [5:03] It prints chip patterns with light at a wavelength of 13.5 nanometers, [5:07] about 14 times shorter than that emitted by previous tools that chipmakers had relied on. [5:13] The shorter the wavelength, the finer the features that a single exposure can print. [5:18] But Intel decided this technology wasn’t going to be ready in time. [5:21] TSMC transitioned to EUV much sooner. [5:24] It put EUV into volume manufacturing in 2019 and ramped it up further on its 5nm node in 2020. [5:32] Intel’s first EUV process did not reach products until 2023, so TSMC had about four more years [5:38] of experience with these machines. Yesterday, we were at the research [5:43] lab getting a preview of 2D materials and CFET and ruthenium interconnects. [5:50] I’m curious about how you decide whether that technology is mature enough for the next node. [5:55] One thing that did also come out of 10 nanometer is we started to define a set of maturity metrics. [6:00] We use those maturity metrics in a process which we call phase gate, where we would say, [6:05] “To go from pathfinding into development, these are the criteria that we need to go hit.” [6:10] There are yield criteria, defect criteria, performance criteria, and we need to hit those [6:14] in order to move to the next set of the flow. If there’s something that doesn’t make that, [6:18] then it misses that, and it goes on to the next technology. [6:21] We focus on the items that are ready and we can run and put into a process, because [6:26] one of the key things is staying on schedule. Staying on schedule is hard partly because new [6:31] transistor designs take decades to mature. Modern chip transistors evolved from the [6:35] planar MOS transistor, demonstrated in 1960. The history of transistors since has been [6:41] the progression from two dimensions into three. Each development that Chris goes on to describe, [6:46] from FinFET to gate-all-around, is a step in that progression. [6:50] So it’ll help to first look at a basic transistor and how its parts have changed over time. [6:55] A transistor is basically a switch. When it’s turned on, it allows current [7:00] to flow between its two ends, which are called the source and the drain. [7:05] A piece called a gate sits on top of the silicon between the source and the drain. [7:11] Applying a positive voltage to the gate turns the switch on, because the positive [7:16] voltage pulls negatively charged electrons in the silicon beneath up toward the gate. [7:22] However, a thin layer of insulation stops them from actually reaching the gate. [7:25] So the electrons collect just beneath that insulation and form a thin conducting path [7:32] from the source to the drain. This is called the channel. [7:36] Remove the voltage and the electrons disperse, the channel disappears, and the switch turns off. [7:41] As transistors shrank, the source and the drain got so close together [7:45] that current could flow through the channel even when the switch was supposed to be off. [7:50] We needed a better way to control the channel and prevent current from leaking through. [7:54] The fix was to give the gate a tighter grip on the channel by touching it from more sides. [8:00] In the original planar transistor, the gate only touches the channel from the top. [8:04] The FinFET transistor squeezes the channel into a thin vertical fin of silicon. [8:09] The gate drapes over the fin, so it controls the channel from three sides. [8:14] The next progression from there was to cover not only the top and [8:17] the sides of the channel, but also the bottom. This technology is called gate-all-around, and [8:22] it slices the channel into thin ribbons, each of which gets completely wrapped around by the gate. [8:27] But getting gate-all-around to work required new materials and new manufacturing steps. [8:31] To build these floating ribbons of silicon, you first sandwich them between alternating [8:36] layers of a temporary placeholder material, which holds the space where the gate will eventually go. [8:42] We use a placeholder because the materials in the real gate wouldn’t survive the processing [8:46] that comes after, which involves baking the wafer at around 1,000 degrees Celsius. [8:52] Once these hot steps are done, chipmakers etch away the [8:55] placeholder, leaving the ribbons suspended. Then they fill the gaps around every ribbon [8:59] with a thin coat of a special insulator called a high-k material, whose purpose is to let the gate [9:04] pull more strongly on the channel. And then on top of this material, [9:09] they put the metal of the gate itself. FinFET was demonstrated in a lab in 1989 [9:14] and reached volume production at Intel in 2011. A gate-all-around transistor had been demonstrated [9:20] a year earlier, in 1988, but Samsung didn’t begin producing gate-all-around chips until 2022. [9:27] So these ideas, FinFET and gate-all-around, were developed around the same time, [9:32] but they reached production a decade apart. I wanted to ask Chris why it took so long to [9:37] get to this current gate-all-around technology. Maybe you can walk me through the process of [9:41] getting into high-volume manufacturing. I want to understand concretely, [9:44] once you have an idea that, “Hey, we’re going to make the channel smaller, we’re going to [9:48] surround it…” All the other problems of material science, figuring out how to not destroy the gate, [9:56] how do they actually get figured out? Why does it take so long? [9:58] Gate-all-around’s a good example, because back in the ’90s we knew of this idea. [10:02] But we knew there were going to be these problems on how you put this [10:05] into high-volume manufacturing. At the same time, there are other [10:08] things like high-K metal gate. There’s strained silicon, [10:13] there’s FinFETs that are out there. It’s a question of when’s the right [10:17] time to go and tackle those? Well, you don’t want to [10:20] tackle something before you have to. If you have these other things that can drive [10:24] performance, you would go and do that. So we went through this path. [10:28] We did strained silicon, high-K metal gate, we did FinFETs, and then it became, “Well, [10:32] we need to do things further. How do we get there?” [10:35] Well, gate-all-around’s really the ultimate transistor out there. [10:38] Maybe it’s time to go and start tackling some of those issues that you have. [10:43] You’re right, now you have to look at how do you put high-K metal gate in with gate-all-around. [10:48] It’s that innovation that takes time. Sometimes you need new materials. [10:52] Sometimes you need a different tool in order to be able to do some of the [10:57] things that you need to go do, and that requires invention from the tool vendors. [11:01] You have to go to the tool vendor and say, “Hey, I need a tool that can do XYZ. [11:04] I need a gas that can deposit this particular material that goes into that. [11:09] I need a heating chuck that has this characteristic to it.” [11:14] All those things take time. Some of it’s iterative, [11:17] where you have to run a gate-all-around transistor and say, “Oh, well, that didn’t work. [11:21] Let me figure out what was wrong with my hypothesis and [11:25] try it again with some different structure.” How has the nature of R&D changed from the era of [11:35] just making planar transistors smaller and smaller and getting the benefits of Dennard scaling, [11:39] to the world we’re in today? Is it just a totally different [11:42] kind of R&D process? Previously it was, [11:43] “Let’s make things smaller, smaller, smaller.” Now you look at all these other facets [11:47] of performance at the same time, and improvements in size don’t come as easily. [11:52] Walk me through whether there was some crucial change in the R&D process at that point. [11:55] If you look at the ’80s and ’90s, yes, it was driven really by Dennard scaling, lithography. [11:59] We just made things smaller, transistors got faster, they got more reliable, [12:03] and it was a very predictable cadence. When we started to hit the 2000s, we saw, [12:09] “That’s not good enough anymore. We need to do something different.” [12:11] To me, it became this golden age of innovation. For each technology node, [12:16] how are you going to provide more scaling? How are you going to provide more performance? [12:21] It drove things like strained silicon. It drove high-K metal gate. [12:24] It drove FinFETs. It drove gate-all-around. It drove backside power. [12:29] These are things that in the ’80s and ’90s you would be like, “Oh no, [12:32] we’re not touching any of that,” because we just continued to have the same process flow. [12:35] We just scaled it, scaled it, scaled it. But for somebody like me who’s a [12:40] transistor junkie, it’s awesome, because now the playbook’s open. [12:46] You can do all sorts of things out there. You can bring in new materials. [12:49] Just look at the number of materials we used to use in the ’90s versus the materials today. [12:52] It’s probably gone up 10X. There’s a lot of innovation. [12:56] There’s atomic layer deposition. You’re controlling this stuff atom by atom. [13:02] So it’s changed a lot how you approach the process. [13:06] Before, it was, “Try to not change anything.” Now it’s, “Take the sledgehammer and start tearing [13:11] the thing up and come up with some new idea.” For 14A, Intel is using a new kind [13:16] of lithography machine: High-NA EUV. It uses the same extreme ultraviolet light [13:22] as today’s EUV machines, but changes the optics. NA, or numerical aperture, is a measure of how [13:29] wide a cone of light the machine’s mirrors can focus onto the wafer. [13:34] The wider the cone you can focus, the smaller the spot that your light can carve. [13:38] Standard EUV machines have an NA of 0.33. High-NA widens it to 0.55. [13:45] So High-NA can print features about 1.7 times smaller in a single pass. [13:51] When features are smaller than the lithography machine can print, chipmakers have to split [13:55] the pattern across several passes, each printing a different set of features. [14:00] The most tightly packed patterns can require two, three, or even four passes. [14:06] Each additional pass takes up valuable time on a machine that costs around $200 million, [14:10] and it introduces another opportunity for defects. High-NA machines cost about twice as much, [14:16] but they can reduce the number of passes that are needed. [14:19] So the question which determines whether they justify their higher [14:22] price is how much more time they save and how much they reduce the risk of defects. [14:27] Now you guys are using High-NA EUV tools for 14A, whereas TSMC has said [14:32] that they don’t make economic sense yet for them. How do you decide whether the next litho tool is [14:39] the one that is ready to adopt or not? High-NA’s a good example of where, [14:45] because of the architecture of our technology versus TSMC’s, we make different conclusions [14:52] off of the same tool set. We use backside power. [14:56] That means that you actually alleviate some of the pitch requirements you have on the front side. [15:01] That allows you to print that directly with High-NA. [15:04] TSMC has to run tighter pitches because they don’t have backside power, [15:08] and they can’t do that with High-NA, so they have to use double patterning EUV. [15:12] So for them, it’s not very helpful. For us, it is very helpful. [15:16] Now at 14A, we’ve left it as an option, and it’s something that we’ll have a discussion [15:20] with the customer on, because there’s some value proposition to it, and there’s some [15:24] complexity that it adds. Chris is referring to [15:27] a feature called backside power. A chip has two different kinds of wiring. [15:31] Power lines deliver electricity to the transistors, and they need to be thick. [15:35] Signal lines let the transistors talk to each other. [15:38] They’re much thinner, but they need to be spaced apart so that the signal from one wire doesn’t [15:42] interfere with the signal from another. In the past, all of these power lines [15:46] and signal lines had to be crammed together on top of the transistors. [15:50] Intel’s newest process moves these power lines below the transistors, to the back of the wafer. [15:55] This frees up space on top, so the signal lines don’t have to be packed as tightly. [16:00] This change makes High-NA worth it for Intel. Without backside power, the wiring is so [16:05] tight that it would require multiple passes to print, even with High-NA. [16:09] With backside power, a single High-NA pass is enough. [16:13] Outside companies can now commission Intel to manufacture chips that they’ve designed. [16:17] They follow Intel’s process design kit, or PDK: the menu of what a given process can build, [16:24] and the rules for building it. Do you need to lock that into [16:26] your PDK right now for customers who are planning on developing on 14A? [16:30] It’s an option in the PDK today, and we’re handling it as a customer-by-customer [16:35] discussion as to whether or not they want to go down that path or not. [16:39] For 18A, there was public reporting that there were delays in or issues with the PDK, [16:44] such that some instructions didn’t work, and it was difficult for people to use [16:47] your foundry to build their chips. Tell me about the process of Intel [16:51] becoming a foundry and then having a PDK that other customers can use to make [16:57] whatever chip they’re making as well. There’s definitely a learning curve to [17:00] how you become a foundry. That’s something that our [17:02] competitors have gone through as well. PDK is a good example of that. [17:05] For decades, we’ve been an IDM. We’ve gone to our product teams [17:09] and shown them our transistor data, and we share that data back and forth, and we haven’t [17:12] had a formal PDK-type process. So that’s a new process that [17:16] we’ve had to implement on 18A. 18A started out not having a PDK. [17:23] There’s definitely a lot of feedback we’ve gotten from the customers as to what they expect [17:27] for quality and maturity of the PDK and what sort of information they want to see in there. [17:33] We’ve tried to incorporate that into making sure that we have a PDK that [17:37] meets our customers’ requirements. That’s where we’ve ended up. [17:40] We’re starting to get PDKs that have this, and 14A will have that from the get-go. [17:45] It has very high quality PDKs. Again, there are maturity metrics for [17:49] what is a PDK 0.5 versus a 0.9 versus a 1.0. We’re constantly going through and taking [17:56] customer feedback and incorporating that into the quality of our PDK. [18:00] For most of its history, Intel’s fabs made only Intel’s chips. [18:04] That could be part of what allowed TSMC to gain an edge. [18:07] Serving many customers gave TSMC more wafers to learn from, more revenue to reinvest, [18:12] and more pressure to hit deadlines. Basically, all enterprise customers [18:16] have a shared set of product requirements that you have to meet if you want to even [18:20] start talking about doing business with them. These are things like SSO, so employees can [18:24] log into your app with their company accounts, or directory sync, so that whenever someone leaves, [18:29] their access gets shut off automatically. These features are harder to get right than [18:33] you think, and the risk-reward for building them in-house doesn’t really make sense: [18:37] a slightly better version of SSO probably won’t accelerate your growth, [18:40] but a broken one will definitely stunt it. WorkOS gives you access to battle-tested versions [18:45] of all the most common enterprise features—things like SSO, SCIM, RBAC, audit logs, and more. [18:51] WorkOS also has versions of these features that are purpose-built for agents, so they can log in, [18:56] grab the right permissions, and take actions within your product. [18:59] All of these features can be plugged in with just a few lines of code, so you can [19:03] add them and get started selling to enterprises. OpenAI, Anthropic, and Thinking Machines—as well [19:08] as more than 3,000 other companies—all rely on WorkOS to meet their enterprise requirements. [19:15] If you want to join them, go to workos.com and tell them that I sent you. [19:20] If a butterfly flapped its wings in the ’60s, could you imagine a world where gate-all-around [19:24] is not even a word people have heard of, an idea people are familiar with, but people are thinking [19:28] of an extremely different branch of the tech tree? How far down the tech tree do you think [19:31] things could be totally different? Could it be that we’re not even using copper? [19:35] If you look at, say, transistors and interconnects, where we’ve gotten to, [19:42] as far as the transistor and gate-all-around and it being the ideal transistor structure, [19:47] was somewhat inevitable. As I said, in the ’90s we were [19:49] already talking about these types of things. Backside power, that one’s pretty out there. [19:54] Even in the ’90s, the idea that you’re going to strip off the entire silicon substrate and put [20:00] lines on the backside, that one is probably something that’s a little bit out there. [20:06] Copper, of course copper wires are the best, so I don’t know how you would end [20:11] up somewhere else besides copper. But you guys are exploring other— [20:14] For some of the very tightest pitches, it’s inevitable that you will replace copper. [20:20] That’s a good example of where you will have another material that will come in there. [20:24] But for the larger lines, I think copper is about where it’s at. [20:28] Once you start to do gate-all-around transistors and you do backside power, [20:33] now you start to enter a very different regime. [20:36] Now you see it’s not, “Hey, there’s just some substrate and you stack everything on top.” [20:41] Now you’ve got a transistor which is floating in interconnect, and you’re like, “Okay, well, [20:45] why don’t I have transistors, interconnect, a little more transistors, more interconnect?” [20:50] This whole 3D stacking that we now do with just discrete chips that we stack on top of each other. [20:55] Now you’re like, “Why can’t I just build an entire structure like this?” [20:59] You see it with memory, NAND, DRAM. They have some incredible 3D structures. [21:06] NAND already does it, DRAM talks about it, but I think that DRAM inevitably [21:10] is going to go there too. A lot of people say, “Oh no, [21:13] we’re not going to do this because we can’t do it in the next five years.” [21:16] Well, come on, let’s put a larger timescale on this. [21:18] Let’s put 10 years, 20 years. In 2045, do you think you could do it? [21:23] Now you start to say, “Oh yeah, I could see us having some pretty [21:25] exotic structures at that point.” We limit ourselves by what we see [21:29] as possible in the next four years. As I’ve always said, when people say, [21:34] “How do you see technology scaling going?”, we have visibility for about four years. [21:38] Then you get out to the four years, and you go, “Yeah, I think there’s something [21:41] we can do another four years out of that.” And you get to that four years, and you’re like, [21:44] “Yeah, I think you can do something.” But if you start to talk about 10 years, [21:47] it becomes hard to say what it’s going to be. Chris’s idea of building upward could start [21:50] with the transistors themselves. Chips use two types of transistor, [21:54] called n-type and p-type, which work the same way, but with the charges reversed. [22:00] Nearly every circuit is built by pairing them up. Today, chipmakers build them side by side. [22:06] The next step is to stack them directly on top of each other in order to save space. [22:11] In principle, that fits twice as many transistors into the same area. [22:15] This design is called a CFET, short for complementary field-effect transistor. [22:20] But every extra layer adds manufacturing steps and cost, and also leads to heat building [22:24] up that doesn’t have a clear way to escape. Because logic consumes more power than memory, you [22:31] can’t do stacks of DRAM that make HBM or 3D NAND as easily with logic, because of the heat issue. [22:38] Is that the fundamental issue over the long run? How you— [22:42] Thermals. There are three things you have when you try to say, “Hey, what limits compute?” [22:49] It’s how fast can you do the switch, so the frequency of the device. [22:53] How much power does it take in order to do that switch, so the power efficiency of it. [22:58] The third one is, how do you dissipate the heat that was generated by doing that switch? [23:02] That’s the thermals piece of it. These are not new problems. [23:07] You can go back 20 years and you can see articles on these three things. [23:10] The question is, thermals… how do you deal with that, particularly when you [23:13] start to talk about these 3D-type devices? There is a need for that sort of system-level [23:21] analysis and simulation tools. I think we’re in its infancy [23:24] because we’ve just started to look at this. It is a limiter, and it will be a limiter, but [23:31] again, these are problems that we can go solve. The problems respond to work, but engineering time [23:36] is finite, and so are the wafers for experiments. Deciding where they go across thousands [23:41] of problems is itself one of the hardest parts of bringing up a node. [23:45] I sat in on one of Intel’s Hot Topics meetings, where those decisions get made. [23:50] I’m here with Kevin Fischer, who was laying down the law this morning at the Hot Topics meeting, [23:54] where you guys were discussing how you’re improving 18A and 18A-P technologies. [23:58] People would come to you with different experiments they were running, [24:01] different ideas they had for improving yield and performance, and then you and [24:06] your integration engineers would tell them what data you needed, how they should proceed, [24:11] how you think they could move things faster. I want people to have a sense of [24:15] the culture at these meetings. One thing I found striking is that this [24:20] is bottlenecking your most advanced node. You want progress to happen fast, [24:24] so you kind of lay down the hammer. I would say the average engineer doesn’t [24:29] understand the stakes or the urgency of how this is going to impact Intel’s bottom line, [24:39] how it’s going to impact our customer. They just have no visibility into those issues. [24:45] They will typically have a certain set of criteria that they want to go capture. [24:52] They’ll hit boundaries of, “I asked for something and someone said no, and I’m done. [25:00] I guess I can’t have this thing that I asked for.” One thing you learn in this industry is that [25:06] you will never have a complete data set. If you want to wait for a complete data set, [25:10] you’ve waited too long. It’s already too late. [25:12] A lot of what I end up doing in those meetings is deciding how much risk we’re [25:18] going to take on a certain decision or not take on a certain decision. [25:23] You need to say, “Look, do we go now? Do we start risking production?” [25:27] Because you’re risking the bottom line. You’re risking revenue. [25:31] I’m worried you’re going to put me in the light of being an ogre because I’m [25:35] putting the hammer down on people. That’s a great reputation to have. [25:39] It’s really conveying urgency. Every day counts. [25:43] Can you walk me through a particular issue that might come up? [25:47] One of the examples you saw this morning is epi nodules. [25:51] Epi is short for epitaxy, which means growing new material on top of an existing one. [25:56] Chipmakers flow gases over a heated wafer, and the gases leave atoms on its surface. [26:02] The crystal structure of the material underneath acts as a template. [26:06] Each new atom lines up with the atoms below it, and the new layer continues the same crystal. [26:11] Chipmakers use epitaxy at several stages of making a chip. [26:14] In the step Kevin describes, they use it to grow the source and the drain as small [26:18] crystals on either side of the gate. During the deposition of our epitaxy, [26:23] we get abnormal growth, a little thing like a tumor. [26:26] It’s growing super fast. That causes problems, [26:30] because one epi will short to the wrong epi and you get transistors not working. [26:35] Then you’ve got to narrow it down to how you’re going to fix it. [26:39] For the past decade, Intel’s chips have had this feature called Processor Trace. [26:43] When you turn it on, it starts recording all the code your program runs, and it captures [26:47] enough detail that you can go back later and reconstruct every single function call. [26:52] Most companies don’t need that level of detail. But Jane Street does: they need to investigate [26:56] specific, fleeting moments in their trading systems—things like [27:00] a delayed response to a network packet. Those events tend to be too brief for [27:04] most debugging tools to catch. So when one of Jane Street’s [27:07] engineers noticed Processor Trace, he started playing around with it. [27:11] And then he and a summer intern turned that exploration into a new tool called magic-trace. [27:16] Magic-trace leverages the output from Processor Trace to give Jane Street a [27:21] history of every function call leading up to a specific moment of interest. [27:25] This project was completely bottom-up—it started just as something that one [27:28] engineer thought would be valuable. And now, traders and developers across [27:31] Jane Street use magic-trace every single day. If you want to work somewhere where you’re trusted [27:36] to pursue the ideas that you think matter most, Jane Street is hiring researchers and engineers. [27:41] Go to janestreet.com/dwarkesh to learn more. One of the pieces that you observed this morning [27:47] was a special clean that we were looking at, which would eliminate the nodule. [27:53] The nodule would deposit, and then we’d get rid of it. [27:56] Some of the other discussion was about the source of the nodule. [27:59] Get rid of the source of the nodule. There’s some issue. How do you [28:04] decide what the source of it is? For the most part, we work highly parallel. [28:08] How do you decide? It’s not always evident [28:10] what the easiest way to fix the problem is, so you work on all the potential fixes. [28:16] Sometimes it’s not the one you expect first. Once we’ve identified it as a primary problem [28:22] for the technology, that’s where this Hot Topics meeting gets involved. [28:27] That’s how we align the resources into those engineering teams so that [28:33] we can accelerate the work. You said that there’s some [28:36] fast-track process where wafers can move through faster if they’re bottlenecking some experiment. [28:40] We have a tiered system of what we call hot boxes in the factory. [28:44] Every grade of hot box goes a little bit faster. It’s just how the factory prioritizes that [28:51] particular lot, that block of silicon that’s running through the factory. [28:55] Our highest grade of hot box, HotBox 1, races through the factory. [29:00] It gets priority at every single tool, but it’s a drag on the entire factory. [29:04] If you had a factory person in here, they don’t like playing that card, [29:09] because you end up using the tools inefficiently so that you can go super fast. [29:16] Think of it as a highway, and you set aside that one lane for the carpool, [29:20] which everyone could use, but you’re saying, “Okay, it’s just the carpool.” [29:23] That’s our HotBox 1. Everyone clear out of [29:26] that lane except for that one experiment, and that one experiment races down the highway. [29:30] Kevin’s job is deciding what goes onto the production line now, but the day before, I [29:35] went to Intel’s research lab with Jack Kavalieros to see ideas that aren’t ready for the node yet. [29:41] We started with wiring. A transistor is only useful once it’s connected [29:45] to others, and on a modern chip that takes more than a dozen layers of metal wire stacked [29:50] above the transistors, called interconnect. Those wires are made of copper, and as they [29:55] shrink, copper starts to run into trouble. Intel is exploring a replacement: ruthenium. [30:01] Ruthenium has higher resistivity, so why are you guys exploring ruthenium for the future? [30:05] Interestingly enough, as you scale the dimensions of those copper wires, you run into challenges. [30:11] For example, copper typically requires a liner in order to deposit the copper to fill those lines. [30:17] Ruthenium is very different in that regard because it’s a material that we can actually etch. [30:23] As such, by etching it, we don’t need that liner. Now you scale those very fine dimensions, [30:30] and if you can trade off that resistive liner with no liner, ruthenium starts to win. [30:37] There is a crossover point where ruthenium will have much better [30:40] conductivity, better resistivity than copper. That’s roughly in the 20-nanometer pitch range, [30:46] which means, if you can imagine, half of the pitch is your metal line, and the other half is [30:52] the dielectric that isolates them. So what is the liner? [30:56] Think of it almost like a glue layer or transition layer that we need in order to deposit the copper [31:02] and have it stick, and have it make that connection to the copper lines below it. [31:05] These are all interlocking copper lines that interconnect to each other. [31:10] But every time you deposit copper, you’ve always had a liner underneath it. [31:15] In the past, that liner may have been a significant [31:17] portion of the entirety of that conduction path. But over time, we’ve scaled it, made it thinner, [31:24] and so copper comes back into play as a contender. One thing I’d be curious to know is how you [31:30] decide that a technology is mature and ready for high-volume manufacturing. [31:36] With 10 nanometer, you were mentioning you guys moved on from copper to cobalt, [31:40] and there were potential issues with that. How do you decide that this [31:44] technology is going to work at scale? The integration of these materials into such [31:48] a complex system as the transistor ecosystem involves many, many different components. [31:54] The scalability is one part, but its ability to integrate is another. [31:59] At the time we made a decision for cobalt, it was the forerunner. [32:02] The results were stronger at the time. But as we work with our ecosystem externally, [32:07] the vendor ecosystem that provides these materials and the tools that we integrate them with, we find [32:13] solutions down the road that may bring copper back in line as being the stronger of the two. [32:20] That’s exactly what happens. Every technology that we go through, [32:24] we will evaluate multiple options. As we get closer to our time horizon [32:30] for delivering a manufacturing-worthy product, we have to make a decision. [32:35] The leading option at the time was cobalt. Now it’s copper again, [32:39] and perhaps in the future it’ll be ruthenium. I’d love to get your thoughts on CFET, basically [32:45] stacking the transistors on top of each other. What is progress like there? [32:50] Can you keep making more and more layers? Is it just two? [32:53] Can you go three, four? How high can you get? [32:55] That evaluation of CFET is currently underway. Not just by us, by our competition. [33:03] Labs externally are looking at it. It is the ultimate in stackability. [33:07] We’re taking transistors that had to be compressed more and more, [33:10] and we’re relaxing that in some ways because we’re going to stack them on top of each other. [33:15] But the act of stacking does not mean that they’re not interconnected. [33:18] What used to be connections on the top or even on the bottom, [33:21] as we’ve seen from our press release, now has to go vertically in between the transistors. [33:27] That’s a new challenge because the aspect ratio of creating trenches and filling those [33:32] trenches becomes more and more difficult. It’s not as straightforward as stacking the [33:37] transistors, because you still have to think about interconnecting them. [33:40] Is the issue there the etch to get that deep hole? Aspect ratio for the etches is a big part of it. [33:45] We’re working with our vendors to evolve on that and to improve that, but it’s also what [33:49] you fill those very tiny spaces with. Because filling can sometimes leave [33:54] air gaps or holes that are never really filled, and that’s not ideal. [33:58] I assume there’s a version of CFET that works inside this lab. [34:02] What is the kind of wafer or process that is working right now? [34:06] Then what’s the next step? What’s the next step after that, [34:08] until it’s inside the full high-volume process? Part of the process of evolving these [34:15] technologies, especially something more complex like an architecture — not just a basic chemistry [34:20] or a material, but a full architecture like CFET — is that we have to make short-loop vehicles [34:26] that can give us faster turnaround. The normal manufacturing process can [34:30] take a month or longer to complete the thousands of steps that it goes through. [34:35] Our goal here is to take unit cells of that process and qualify them. [34:41] We take advantage of short-loop vehicles that can give us electrical parameters, [34:47] chemical parameters that can resolve some of those challenges, those speed bumps. [34:52] Once we’ve resolved them, then we combine them into a more complex test vehicle. [34:58] What you would find in here is something very simple. [35:01] You might be making a diode, you might be making a capacitor, which are components of the transistor. [35:08] As those evolve and become stronger, better performing, you combine them to make the next [35:14] stage, which might be the transistor itself. In the CFET example, you might not choose to [35:20] do four ribbons on top of four ribbons. You might just choose to do one on one, [35:25] because naturally the aspect ratio of dealing with something that [35:29] much taller becomes more and more challenging. So we would have a simplified version of a CFET, [35:35] which has only one wire for the NMOS and one wire for the PMOS. [35:40] That simplifies our job, but it still helps us evaluate the stacking of devices [35:46] and how they will interconnect. But are the feature sizes here as [35:49] small as they will be eventually? Or are the feature sizes bigger? [35:52] Oh, absolutely. In some cases, at least as small. For example, you’ve heard of 2D materials, [35:59] these transition layer dichalcogenides, as they’re called. [36:03] They’re very, very thin materials. They’re essentially one monolayer [36:07] of atoms that we deal with. Those depositions can happen in this lab. [36:12] We can evaluate those films in terms of conductivity, our ability to contact them, [36:17] our ability to modulate that conductivity, which is what the transistor does. [36:22] So yes, we do have the ability to not only deposit films that are very small and thin to the [36:30] atomic scale, but also print very small features. We have EUV technology, or E-beam technology, that [36:38] can allow us to print very small features similar to what we will eventually make in production. [36:43] I guess I don’t understand intuitively, lacking the context in this process, [36:51] if you have the features that are as small for a working CFET right now. [36:57] Why will it take 10 years for it to be in my phone? [37:01] I understand that there’s a process, but why is it such a long process? [37:05] The answer is slightly different when you’re dealing with an architecture [37:09] like CFET versus a novel material. Materials have, of course, the [37:14] challenges of being deposited, etched, removed. Their compatibility with other layers above and [37:21] below, all those things have to be researched first before you put them in a production line. [37:26] An architecture may seem like a simple evolution. “Oh, you’re making nanoribbon [37:31] transistors next to each other. What’s wrong with just stacking them?” [37:35] But the act of stacking them, of course, increases the aspect ratio for etches, depositions, cleans, [37:41] and the technology may simply not be ready yet. But if you’ve already made it here, there’s a [37:47] version of the technology that’s ready, right? Correct. We’ve made a simplified version that [37:52] may not be an advantage over our current side-by-side technology of nanoribbons, [38:00] but we need to evolve it to make it maybe two nanoribbons, or to add the right type of [38:04] metals and dielectrics, in order to extract the maximum performance out of that device. [38:10] Got it. So it’s like a long tail of— There’s a thousand different steps that [38:14] all have to come together in a very unique way to make the performance compatible or actually [38:20] supersede the prior technology. Where do the ideas tend to fail? [38:24] You have 20 ideas like 2D materials. What is the way in which you decide [38:29] this is actually not worth pursuing further? Sometimes we discover fundamentals about the [38:37] material that will be incompatible with the rest of the processing that we do. [38:44] The first level of experiments may simply be very simple depositions. [38:48] You say, “Okay, I can deposit the film, I can look at it, I can measure it. [38:53] But the moment I try to make a contact to it, nothing sticks.” [38:56] It could be something as fundamental as the adhesion. [39:00] The next step in the process simply has no way to adhere to the material. [39:06] So you may rule out a material because of something as simple as that. [39:10] More complex challenges might be that the subsequent processing may [39:16] have gaseous interactions with downstream steps. For example, I’ve deposited the film, I’ve capped [39:23] it with other materials, but they’re not hermetic. So my third or fourth or fifth step in the [39:30] process may actually still interact with it and change its properties. [39:34] That makes it unstable, and now we have to find better hermetic sealing for that process. [39:40] If we don’t find a way to control it, then it’s a dead end for us. [39:45] Stacking transistors is still in the research lab. Stacking whole chips is already in production, [39:50] and it tackles a different problem: how separate chips communicate with each other. [39:55] Modern computers are divided into multiple parts, each optimized for a different task. [39:59] For example, Nvidia’s Blackwell data-center GPU joins two huge processor chips and surrounds them [40:06] with eight stacks of high-bandwidth memory. These chips have to constantly send [40:10] data back and forth with each other. And in AI, the speed of that traffic, [40:15] not the raw computation itself, is often what limits how fast the workload finishes. [40:20] Imagine two chips side by side, communicating through their facing edges. [40:24] If you double each chip’s width and length, you’ll have four times the area for circuitry, [40:28] but only twice the edge length for connections. This is the area-versus-perimeter problem. [40:33] As transistors become denser, a chip’s ability to do computations increases [40:37] faster than its ability to move data around. The industry has known about this problem [40:42] for years, so multiple technologies have been invented to address it. [40:45] The completed circuits must undergo two last operations: bonding and packaging. [40:51] Once a chip is made, it still has to be connected to other chips and to the rest of the computer. [40:56] That step is called packaging, and it has changed a lot in the last few decades. [41:00] At a high level, you can think of the evolution of packaging like this: initially, [41:04] chips were laid out side by side. Wires connecting them went out [41:07] the side of one chip to another. To allow for more communication [41:11] density, the industry introduced a shared piece of silicon, called an [41:15] interposer, for multiple chips to sit on. A chip can talk to other chips through the [41:19] wiring that runs directly through the interposer. This type of packaging is often called “2.5D”. [41:25] Another way to increase connection density is to bond chips directly to one another. [41:30] This allows for shorter connections between chips, but the early versions of this idea used solder [41:35] bumps, which are bulky and increased resistance. It would be better to skip the solder and fuse [41:41] the signal wire connections of the two chips directly to each other. [41:45] This is called hybrid bonding, and it is one of the technologies the [41:48] semiconductor industry is investing in the most. Hybrid bonding works by aligning the copper [41:53] interconnects of one chip with those of another. Then these chips are pushed together and heated [41:58] so their interconnects expand and bridge the gap between the chips. [42:01] This process makes the insulating surfaces around the copper bond as well. [42:05] And so by removing the solder bumps, you end up with much denser connections. [42:09] But the reason this technology is only now entering volume manufacturing is because [42:12] it took a while to iron out the alignment and defect challenges that it introduced. [42:16] In the packaging lab, I asked Tyler Osborn, a director in Intel’s advanced packaging [42:22] technology development group, how they put this into practice. [42:25] Intel has spent over 50 years optimizing its CPUs for speed. [42:28] But lots of these optimizations—like caching and branch prediction and [42:32] speculative execution—reduce predictability. The exact same instructions can take four [42:36] cycles to execute one time and 300 the next. When you stack billions of instructions together [42:41] and execute them across multiple threads and cores, these non-determinisms compound into [42:45] all sorts of hard-to-reproduce bugs. If you work on serious systems, [42:49] you’ve definitely experienced this. Antithesis solved this by doing something a bit [42:53] crazy: they built a 100% deterministic computer. They identified every single door in Intel’s x86 [43:01] architecture where non-determinism could leak in—network packets, disk reads, [43:05] temperature sensors, even time itself. And they either welded each of these [43:09] shut or slotted in a controlled simulation. This deterministic computer is just a foundation. [43:15] On top of it, Antithesis built a testing platform that compresses [43:18] years of production hardening into minutes. It runs your software through thousands of [43:22] parallel worlds, injecting faults and intelligently steering each one [43:26] towards a one-in-a-billion failure that you’d never be able to test yourself. [43:30] This determinism is what’s behind all the other insane Antithesis features that I’ve [43:34] mentioned over the past few episodes. It’s what lets you reproduce any bug [43:38] and time travel to any point in the test run. Most importantly, it’s what lets you—or your [43:42] agents—trace every failure back to its root cause. Go to antithesis.com/dwarkesh to learn more. [43:53] Two different ways you could do hybrid bonding: die to die and die to wafer. [43:59] Maybe you can talk about the advantages of both and which one actually practically works better. [44:03] Sure. Around Intel, what I think you’re referring to as die to die, [44:07] we typically call wafer to wafer. We actually take a full wafer and [44:10] another wafer and bond them together. That’s an approach that’s really popular [44:14] right now in the CMOS image sensor industry. In fact, it basically dominates it. [44:19] It’s being looked at for other things like memory stacking. [44:22] People have published ideas about all kinds of stuff. [44:24] One of the challenges with that, though, is that you need dies that perfectly match each other, and [44:29] are perfectly left-handed and right-handed, so you have to be able to bond exactly one to the other. [44:35] One-to-one die size is a challenge. If they’re not the exact same design [44:39] device on top and bottom, that’s a problem. With wafer to wafer, it’s challenging to make [44:43] sure that you have wafers that match really well in terms of the sort. [44:46] So sort good array here versus sort good array here. [44:49] If they match exactly — good die and bad die all match — I can get 100% yield [44:53] of that operation of the good dies. But the chances of that are very low. [44:57] There’s going to be some randomization of the two, and whatever that randomization is, [45:01] will be loss of good bonding to bad. Whereas with chip to wafer, [45:06] I can dictate the terms. I can singulate and have known good dies [45:11] that I’ve tested at the chip level, and then only bond known good to a known good base position. [45:16] Do you think then chip to wafer is the way that you’ll do hybrid bonding in the future? [45:19] I think we’re going to do both. We definitely have the capability to do both. [45:23] It’s really customer and architecture driven, but certainly chip to wafer in [45:26] the logic-to-logic space makes a lot of sense. You were explaining that going from advanced [45:31] packaging to hybrid bonding, the size of the pitches is decreasing. [45:34] How much further could that go? That’s a wonderful question. [45:38] Historically, like we were saying, 15 years ago first-level interconnect [45:41] was 130-150 micrometer pitch. Today in HVM, we’re doing 25 [45:46] micrometer pitch in Foveros. Here we’re doing sub-10, [45:50] but there’s already been literature out there. In fact, the biggest conference every year [45:54] in packaging is the IEEE ECTC conference that happens in May. [45:59] There was a paper there this year showing reliability data on a [46:03] 0.45 micron pitch hybrid bonded device. So you can imagine that’s a whole other [46:08] order of magnitude in density again from where we are right now in HVM. [46:14] That scalability has already been proven. So I see a long runway there. [46:18] Within interconnect, within a single wafer, how far separated are they usually? [46:23] In the back end of the fab, you can imagine the few layers below packaging are typically around [46:30] one micron to a half micron in size. So if you can push packaging down [46:35] to 0.5 microns or below, you can almost think about taking layers off the top of the die and [46:42] connecting a lower layer within the silicon to another lower layer within the silicon. [46:46] That’s really where the beauty of hybrid bonding happens. [46:49] You could think someday about even having reduced interconnect layers on both sides [46:53] that we can bond together and have less total IR drop between the two transistor layers. [46:59] It’s really cool to think about where that could go once we get into those regimes. [47:04] Actually, I am very curious about… For AI, it makes sense why hybrid [47:07] bonding is so powerful, because then you can get higher bandwidth to the memory. [47:11] But you were saying there are issues with heat and everything. [47:14] What is the advantage for non-AI applications of hybrid bonding? [47:17] Excellent question. There are companies out there that are looking at it for [47:21] non-AI applications, even in client devices. One of the big things I think it can help [47:28] with there is, number one, obviously the same raw interconnect density, especially [47:32] between something like a CPU and a GPU. But the other one is around power. [47:37] Like we talked about before, as you get to finer and finer interconnects, [47:41] you can reduce the total power consumption, in picojoules per bit, for that interface. [47:46] With hybrid bonding in those applications, you could think about that as another way [47:49] that packaging can help reduce the total system power budget. [47:53] That gives you lots of benefits: lower power, less heat, for the same benefit [47:58] in terms of actual electrical performance. So far, this has been about making better chips. [48:02] The other half of the question is how many chips the industry can make if AI labs are [48:07] willing to pay for far more of them. I’m getting a chance to talk to [48:11] Pushkar Ranade, who is the CTO of Intel. I’m very interested in understanding how [48:16] the fact that the entire industry has to rely on the same suppliers bottlenecks [48:20] your ability to ramp up production. For this EUV tool, ASML produces [48:24] fewer than 100 of them a year. They don’t plan to produce more [48:28] than 100 a year, or significantly more, even by the end of the decade. [48:31] That has to be split between you, between TSMC, between all the memory makers who [48:35] are ramping up production, like SK Hynix. How does that limit your ability to scale [48:38] up to all this demand? It is a limiter. [48:42] We have to make the most of the capacity that we already have installed. [48:45] We’ll try to increase the output from our existing fleet of tools. [48:50] But EUV or ASML is not the only bottleneck. It is definitely a bigger bottleneck than [48:56] some of the other tools, but to a large extent, we’re seeing [49:04] all equipment seeing tremendous supply shortage. Even though there are multiple providers of other [49:10] tools, once you lock into a process flow — let’s say 18A, which is a mature process [49:17] now — we need a specific tool. We can’t just go and get a [49:22] different tool for the same process. So we’re locked into that one tool, [49:27] one supplier, and we rely on that. What lessons does this give for [49:32] 14A in terms of how you structure it? By 2028, it’s going to be such a crazy world. [49:36] How do you structure things in such a way that you have flexibility in ramping? [49:40] The way to do it — and we’ve been doing it, and generally everybody does it — is [49:44] you try to maintain as much fungibility as possible going from one node to the next node. [49:48] Going from 18A to 14A, maybe you would say 80% of the tool set can be reused. [49:54] Then, of course, 14A would require some new capabilities because it’s a denser geometry, [50:01] so it would require some unique tools. Do you have a sense of what the ultimate [50:05] bottleneck is on how many wafers you guys could produce a month, even if you were to decide [50:11] to invest infinity money into doing CapEx? Given the existing constraints, let’s say we had [50:17] to maximize the output from a given footprint of tools, then I think it’s incremental, because the [50:25] process today is already yielding pretty high. If your yield is already pretty high, [50:31] getting every 1% extra yield is extremely hard because it’s already a finely tuned process. [50:38] Are there enough tools in the world so you could 10X the amount of wafers you’re [50:40] producing at the leading edge? Not 10X, but probably 2X, yes. [50:45] That’s quite interesting, because the AI industry for a decade has [50:49] been 3Xing compute year over year. You’re saying that just can’t continue. [50:55] Unless the entire supply chain — starting from the equipment suppliers, their suppliers, [51:01] their sub-suppliers — unless everybody produces more, you can’t increase the output. [51:07] Just to give the audience a sense of how big the AI demand is and how well it monetizes the [51:13] products you guys are producing: you can crunch the numbers, and the numbers seem to suggest [51:18] that just a couple billion dollars of CapEx on Intel’s account results in enough chips — or the [51:24] logic for enough chips — to produce, say, $100 billion of revenue for the AI model companies. [51:30] Of course, there are so many other players within that stack. [51:32] There’s also memory and other things. But it’s crazy that a couple billion [51:38] dollars of CapEx, which can be amortized over many different years, produces $100 billion [51:44] of revenue every single year. That seems to suggest that at [51:47] some point that should percolate down. At some point, the AI labs could just say, [51:52] “We’ll just buy everything. Produce as much as you can. [51:54] We’ll guarantee future income streams.” There are early signs that could [51:59] actually be happening already. The demand signals are just so high. [52:04] But I think you were alluding to how the value is accumulating at the top of the technology stack. [52:13] What is essentially happening is we moved from a fully vertically integrated industry 30-40 [52:20] years ago, maybe longer, to a very horizontal industry, where you have foundries, you have [52:26] equipment makers, you have their suppliers. Today, every hyperscaler is designing their [52:34] own chips, and the scale of the hyperscalers is so large. [52:38] Some of the model companies, for example, their demand is so high [52:44] they could easily consume an entire fab’s worth of silicon on their own, or multiple fabs’ worth, [52:53] and they definitely have the capital to fund that. So in some sense, we are moving from a horizontal [53:01] world again to a pseudo-vertical world. It’s not monolithically vertically integrated, [53:10] but it’s kind of virtually vertically integrated. What is the nature of economies of [53:17] scale in this business? If you look at how many [53:21] wafers at the leading edge TSMC versus Intel is shipping, it’s upwards of 3X for TSMC. [53:28] What kinds of advantages do you get at this point from economies of scale? [53:32] Or is it that once you reach a certain point, the economies of scale get weaker? [53:36] That’s a very important question. This entire business just [53:41] relies on economies of scale. If you look at all the advanced manufacturing [53:49] companies out there, in semiconductor foundries the scale economics is probably the purest. [53:56] The reason for that is the fixed cost is just so incredibly high. [54:02] Once you build a fab, like 80% of your cost structure is fixed. [54:07] What that means is every extra percentage of utilization is adding far more in revenue. [54:16] So it’s extremely important. We’ll fight for every extra [54:19] percent of fab utilization, but also every extra percentage of fab output. [54:25] Let’s say I’m making some wafers today and the yield is 60%. [54:30] If I improve the process and the die yield becomes 65% or 70%, it’s not a linear advantage. [54:38] I’m getting way more output for the given footprint. [54:42] So there’s always room to improve the economies of scale. [54:45] That’s one of the reasons why you’re seeing so much consolidation in this business. [54:53] There are only three foundries left at the advanced node for that exact reason. [54:59] Along the way, many companies just stopped manufacturing. [55:04] I don’t know if you’ve seen… There’s a chart where 40 [55:07] years ago there were like 20 foundries. Over time the number of foundries kept [55:13] diminishing until today there are only three. What is then the concrete master [55:17] plan to catch up to TSMC? Even though TSMC is ahead, [55:21] there’s so much overflow demand at their leading edge, where N3 is now majority AI [55:26] accelerators and maybe majority Nvidia alone. There’s all this demand for CPUs, for other [55:32] things, which are also, by the way, needed for AI. There’s this humongous influx [55:36] in demand for CPUs because of AI. How do you see this opportunity right now, [55:39] where Intel’s a few years behind, while TSMC is just way oversaturated? [55:44] Catching up to TSMC has multiple facets. The catch-up that we need to do is in scale. [55:52] Like you said, they’re just a much larger wafer manufacturer today than we are, [55:58] and even bigger than what Samsung is. Catching up in scale will be a gradual process. [56:08] If you meant catching up in terms of just the technology, I think we’re already there. [56:18] We might be a few percent off on performance or power or area density. [56:28] But this sort of benchmarking, where one foundry is ahead or one foundry is behind, [56:38] makes sense when you’re a whole generation behind or two generations behind or ahead. [56:45] That’s when it makes a meaningful difference in your die output or your [56:49] die area or functionality like power. But if you’re within a few percent, [56:59] you’re splitting hairs at that point in time, because it’s not very unidimensional. [57:06] It’s not just about density, it’s not just about raw performance. [57:11] Different applications require different vectors. You can be off by a few percent, [57:17] but you need to be on time. Your execution needs to be [57:20] such that your yields are very high to support very large and very rapid ramps. [57:27] That actually is more important than catching up on a few percent in performance or area. [57:33] I was looking at some SemiAnalysis numbers that seem to suggest that in [57:36] terms of transistor density, 14A — which will come out in 2028 — would be comparable to N2. [57:43] First of all, I would dispute your benchmarking. [57:47] But like I said, it’s important to be generally in the right ballpark and be very predictable. [57:56] Also, it’s not unidimensional. We don’t build one type of [58:01] transistor, let’s say 14A or 18A. You build a few different types of transistors. [58:08] There’s a low-leakage transistor, there’s a high-performance, high drive current transistor. [58:13] You’re building SRAMs. There’s a high-density SRAM, there’s a high-performance SRAM. [58:18] There are many other functionalities like analog circuits, RF circuits. [58:24] It’s the sum of all of those that makes a technology competitive. [58:29] I guess that makes the CapEx you do right now even more important. [58:34] TSMC is on track to do around $50 billion in CapEx this year. [58:38] You’re on track to do around $20 billion. If the tools you’re buying right now will [58:41] determine who can service all this crazy AI demand that’s coming up, it makes the difference [58:46] in CapEx right now even more important, or for the US versus other countries. [58:52] Yes, very much. It’s a little bit of an unfair comparison between us and TSMC today, [58:58] just because today they’re a foundry for basically everybody and we’re largely a foundry for Intel. [59:05] We’ll become a foundry for others. In due course, our CapEx will also grow. [59:11] Intel started as a DRAM business in the late ’60s. You guys were producing DRAM, which you sold off. [59:19] A couple years ago, you sold off your flash business. [59:25] Thoughts on that? For context for the audience, these are [59:28] now multi-trillion-dollar industries because they’ve just exploded as a result of AI demand. [59:36] Clearly, in hindsight, probably not the smartest time to sell off a flash memory business. [59:42] There were good reasons why we did that when we did. [59:46] Clearly, nobody could see this enormous demand. But today, the world will eat up as much compute [60:00] as can possibly be made, and it’ll eat up as much memory as can possibly be made. [60:06] I would argue that the supply crunch is larger for memory today than it is for compute. [60:12] Can I summarize what seems to me the takeaways from your projections? [60:16] You can tell me if that’s correct. [60:17] That marginal production can increase actually very fast — on the scale of 12 [60:22] months — but the amount of increase up till the end of the decade is extremely limited. [60:27] Production could be higher next year than what people are forecasting, but production [60:30] in 2030 is not going to be significantly higher than what people are forecasting. [60:33] Unless the entire supply chain ramps up production very quickly. [60:36] We’re already in the middle of ’26, so there’s not that many years until the end of the decade. [60:42] Given the lead times… Let’s say you place an [60:45] enormous order for tools today, and you’re looking at 18 months to get those tools. [60:52] You’re already into basically ’28. From that point on, if you have to [60:57] build a new shell, build a new fab, you’re basically looking at the end of the decade. [61:02] I think it’ll be interesting to discuss the partnership you guys have with Elon on Terafab. [61:07] What’s going on there? Well, Elon’s publicly talked [61:14] about his desire to build a fab. We either build the Terafab or [61:19] we don’t have the chips. And we need the chips, [61:23] so we’re going to build the Terafab. Sort of the same thinking. [61:26] He’s seeing just an enormous increase in demand for silicon, for compute and for memory. [61:34] I think he came to the conclusion that his own businesses are going to require a lot of silicon. [61:42] He thought maybe he should just do it all on his own. [61:46] But unlike building a car, for example, this is such an intricate and complicated [61:52] process that we thought we could work together to help accelerate his bringing up his fab. [61:59] But because of the bottleneck at the tool level, it seems like the net [62:04] amount of silicon in the world won’t increase. It’s just that maybe if somebody were to start [62:09] a new fab, they would get access to guaranteed supply in a way that they wouldn’t have if they’re [62:14] working with another person’s foundry. It’s not just tools. [62:18] A fab does require a lot of power, a lot of water, a lot of consumables. [62:24] There are many other input variables as well. But those can be scaled in the [62:28] way that tools cannot. Some more than others, but yes. [62:34] In one sense, yes, we need a lot more equipment. But it is true, we also just need a lot more raw [62:42] fab space, raw clean room capacity. If you think of a foundry like Intel, [62:48] which has to build these expensive facilities and buy expensive tools, I wonder what you think the [62:55] economics of that fundamentally could look like, whether it could get more economical, [62:59] whether it could scale faster. Like I described earlier, [63:03] this is an extremely capital-heavy business. If you just plot how much it costs to build [63:11] a fab over the last 20, 30, 40 years, I think it’s doubling every 4-5 years. [63:19] Even inside the fab, if you look at the cost to do lithography, which is the most [63:24] expensive module — just patterning — that itself is doubling at more than that rate. [63:31] Today, a High-NA EUV scanner and all its associated equipment costs like $400 million. [63:41] So what does that mean? If that rate were to continue, [63:44] if you just draw the line, does that mean four years from now the cost of patterning [63:50] is going to be like $800 million? It doesn’t really make sense. [63:58] A very interesting thought exercise is to ask, are there things that could be [64:05] just very radically different that we could do today that we perhaps couldn’t do 20 years ago? [64:14] This is a very risk-averse industry for very good reason, for exactly that reason. [64:19] You put in tens of billions of dollars, and you really don’t want to take any risks. [64:25] You want to keep doing things the way they’ve been done for literally decades. [64:29] This is not just true of semiconductors, but everything really. [64:33] If you’ve just kept on doing that for decade upon decade, you just become indoctrinated. [64:42] There are engineers who probably work at Intel who are new, who come in and they’re taught, “This is [64:48] how the fab works, this is the process flow.” They just take that as gospel. [64:53] That’s just how it is done. But is that really the best [64:57] way to build a chip today? It’s a really valid question. [65:02] I’m very curious what you’re hinting at, because it could be anything from figuring [65:06] out ways to use fewer litho passes and economize on this expensive component, to maybe we need to [65:13] rethink the transistor. What is the level of— [65:19] All of the above. Transistor architecture is evolving. [65:25] Just the silicon transistor has continued to evolve over 30, 40 years, and that will continue. [65:33] You’ve seen the evolution from the planar transistor [65:36] to FinFETs to now gate-all-around transistors. There’ll be more. That roadmap exists, it’s pretty [65:44] well defined, with a lot of people working on it. But there are things like… [65:51] Do you really need a clean room today? Do you need the infrastructure to be as [65:58] sophisticated, as complex as it is today? Surely one can run an experiment where you [66:05] have people eating hamburgers and smoking cigars in the research fab and see what happens to yield. [66:12] That would be a great experiment to run, but no incumbent — Intel or TSMC or Samsung — would [66:20] want to willingly do that. That’s what I meant by this. [66:26] It’s a very risk-averse business, for good reason. Every one day lost in productivity is… [66:32] I don’t know how many dollars. But you save so much money in [66:35] not having to build clean rooms in the future. But it’s really the risk, the fear of the unknown. [66:41] Nobody is going to willingly take that risk. That’s why I think sometimes it’s good to just [66:49] start with a clean slate and rethink everything. The same thing applies to chip design, by the way. [66:59] Many of the ways we do CPU design were probably locked in 30 years ago. [67:06] Does that mean it’s smart to still do it the same way? [67:11] Probably not. But this is a very complex problem. In chip design, I guess the capacity to take [67:25] risk is maybe higher. This one, less so. [67:29] But given where the economics is today, I think it’s a very valid question to ask. [67:36] Maybe there’s a smarter way to do this. To close out, maybe we’ll start off at [67:40] the same question we began the interview with, which is, how does Intel respond to this crazy AI [67:47] demand that’s incoming and has already arrived? It sounds like what Intel ought to do — if the [67:54] ultimate bottleneck is that you guys already have these foundries, you already have the [67:58] ability to expand these foundries, but what you will eventually lack is the tools from upstream [68:05] in the supply chain — is to just raise as much capital as possible right now. [68:10] The same way that Nvidia has locked down memory and other components for reportedly hundreds [68:15] of billions of dollars worth of commitments that it’s made, Intel should maybe do the same thing: [68:21] make all these commitments so that over the coming years, the US is in good position to [68:28] have the bulk of semiconductor manufacturing at the most advanced levels happening here. [68:32] You’re suggesting we should be buying a lot more tools, right? [68:35] Yeah, because it sounds like otherwise in a couple years you’d just be in a position [68:39] where you’re like, “Oh man, we could be making trillions of dollars right now, [68:42] but all the tools are in Taiwan.” Yes, that’s a very valid question. [68:47] Had we known what we know today, we would have invested more like a year ago. [68:52] Knowing what we know now, I think we’ll be investing more.