Stanford Online
Traditional server makers leave enterprises running PC-era hardware with opaque firmware, forcing buyers back to physical racks that integrate open software down to the silicon.
AI-assisted summary of Stanford Seminar - The Soul of a New Machine: Rethinking the Computer — original source. Check the original for full context.
Source published:
Key ideas
- Enterprise data center hardware has largely stagnated as rebranded commodity PCs, whereas hyperscalers have moved to custom, rack-scale designs using DC busbars and centralized power shelves. (7:44)
- Proprietary BMC firmware and legacy BIOS implementations introduce critical security vulnerabilities and telemetry black holes, making a clean-sheet open firmware model essential. (23:25)
- Oxide Computer Company was launched to deliver an integrated, rack-scale computer targeting on-premises enterprise workloads with modern open-source firmware, Rust, and RISC-V. (61:45)
- Cloud economics frequently compel scaling SaaS companies to repatriate compute workloads to on-premises infrastructure as public cloud hosting expenses directly hit cost of goods sold (COGS). (74:00)
Detailed notes
## Background Published by Stanford Online on YouTube on March 4, 2020, this Stanford Seminar features Bryan Cantrill, co-founder of Oxide Computer Company, delivering a talk recorded on February 26, 2020. The session outlines how mainstream server hardware has stagnated in a bygone era of PC architecture while hyperscalers have moved ahead, presenting Oxide's vision for a clean-sheet, rack-scale server machine built using open firmware, RISC-V, and Rust.
## TL;DR Bryan Cantrill traces the evolution of server computing to argue that modern enterprise servers remain glorified, fragile desktop PCs saddled with legacy baggage, opaque proprietary firmware, and insecure baseboard management controllers. While hyperscalers engineered custom rack-scale architectures to solve these problems, mainstream enterprises face steep operational hurdles and economic cloud lock-in without access to comparable hardware. Cantrill presents Oxide Computer Company's strategy to build a unified rack-scale machine that places the computer's boundary at the virtual machine provisioning API. He demonstrates how modern technological shifts—specifically Rust's memory safety, open-source firmware, RISC-V soft cores, and open EDA tools—make an auditable, vertically co-designed computer achievable.
## Atmosphere & style Delivered with Cantrill’s signature rapid-fire cadence, biting wit, and unbridled technical passion, the talk feels like an exhilarating manifesto delivered from the low-level systems engineering trenches. The mood balances laugh-out-loud irreverence—taking aim at legacy BIOS vendors, DOS baggage, and vendor spy-chip distractions—with a profound reverence for computer history and engineering lore. Watching it feels less like a dry academic seminar and more like a passionate call to arms for systems programmers ready to tear down decades of accumulated architectural compromise.
## Bulletin - [07:44](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=464s) Enterprise data center hardware has largely stagnated as rebranded commodity PCs, whereas hyperscalers have moved to custom, rack-scale designs using DC busbars and centralized power shelves. - [23:25](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1405s) Proprietary BMC firmware and legacy BIOS implementations introduce critical security vulnerabilities and telemetry black holes, making a clean-sheet open firmware model essential. - [01:01:45](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3705s) Oxide Computer Company was launched to deliver an integrated, rack-scale computer targeting on-premises enterprise workloads with modern open-source firmware, Rust, and RISC-V. - [01:14:00](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4440s) Cloud economics frequently compel scaling SaaS companies to repatriate compute workloads to on-premises infrastructure as public cloud hosting expenses directly hit cost of goods sold (COGS).
## Key takeaways - [07:44](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=464s) Modern commercial enterprise rack servers remain fundamentally commoditized personal computers burdened with legacy PC baggage like emulated interrupt controllers and VGA ports. - [13:22](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=802s) Hyperscalers successfully decoupled from PC architecture by engineering rack-level architectures like OCP Tioga Pass with DC busbars and blind-mate sleds. - [17:20](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1040s) Proprietary firmware obscures vital hardware telemetry, such as discarding correctable single-bit memory error warnings prior to uncorrectable fatal panics. - [23:25](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1405s) Baseboard Management Controllers (BMCs) present massive attack surfaces because they operate Linux and U-Boot, master the host PCIe bus, and expose internet-facing network interfaces. - [26:19](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1579s) Host boot firmware should adhere to a minimal role: initialize the hardware, hand execution cleanly to the operating system, and exit memory completely without persistent runtime traps. - [29:22](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1762s) True rack-scale computer design requires unified co-design across top-of-rack networking switches, compute blades, and shared power shelves rather than simple server stacking. - [32:15](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1935s) The functional abstraction boundary of the modern enterprise computer has shifted to the API endpoint used to provision a virtual machine. - [36:50](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=2210s) Speculative execution vulnerabilities such as Spectre and Meltdown forced the computing industry to prioritize hardware roots of trust and verifiable firmware attestation. - [40:42](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=2442s) The maturation of open electronic design automation (EDA) tooling, HDLs like Bluespec and Chisel, and the royalty-free RISC-V ISA enables rapid custom silicon and soft-core integration. - [55:28](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3328s) Rust provides the deterministic performance and low memory footprint of C while preventing memory safety and integer overflow vulnerabilities at compile time. - [58:06](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3486s) A naive Rust implementation outperformed hand-tuned C by 35% primarily due to standard library cache locality advantages with B-tree structures over traditional binary search trees. - [01:00:07](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3607s) Rust binaries can easily fit within 512 KB to 640 KB of embedded FPGA RAM, demonstrating the viability of writing modern firmware and embedded operating systems safely. - [01:12:04](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4324s) High-performance virtualized enterprise workloads still necessitate x86 microprocessors, whereas RISC-V shines in bounded embedded service processor roles. - [01:19:20](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4760s) High-speed motherboard trace propagation and DIMM training physics demonstrate why transparent, auditable boot firmware is necessary for operational reliability. - [01:23:07](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4987s) Enterprise engineering teams increasingly rely on open software layers and containers to decouple their software stacks from proprietary public cloud service lock-in.
## Detailed walkthrough ### [00:11](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=11s) Setting Expectations: Not a Book Club
Bryan Cantrill, CTO of Oxide Computer Company, opens by clearing up a misunderstanding circulating online. His friend Jon Masters (formerly of Red Hat, currently at Nuvia) had tweeted a link to the seminar citing only the pre-colon title: "Bryan's gonna talk on The Soul of a New Machine." This prompted a noticeable portion of the internet to assume Cantrill was hosting a book club on Tracy Kidder's classic 1981 book, *The Soul of a New Machine*.
Cantrill clarifies that while he holds Kidder's work in the highest regard, today's talk is not a book review. Kidder's book documents the intense engineering effort behind the Data General Eclipse MV/8000 (code-named "Eagle") in the late 1970s and early 1980s. Cantrill uses the title as homage, seeking to channel that era's passion, fervor, and engineering depth into modern server hardware:
> "I love it; it's an amazing book if you haven't read it. It is truly... the Iliad or the Odyssey; it is the literature of our domain, but I'm only using it as a title."
[01:36](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=96s) The Genesis of the Server: The IBM 709 and Mainframe Scale
Cantrill introduces the IBM 709 as the candidate for the very first real "server." Although earlier machines existed, the 709 was the first system possessing enough raw capacity to support time-shared computing. Demonstrated in the early 1960s with the Compatible Time-Sharing System (CTSS), it marked the birth of server-side computing—a paradigm where computing happens at a physical distance, out of sight, reach, and direct sensory contact of the operator.
The sheer scale of these vacuum-tube systems highlights the rapid physical transformation of computers. Displaying data from an early comprehensive survey of U.S. computer installations, Cantrill calls attention to a specific IBM 709 installation at Hughes Aircraft. In an era before transistors eliminated massive heat and power overheads, these systems demanded enormous facilities:
* **Power consumption**: The IBM 709 pulled 205 kW (compared to a modern data center rack, which draws roughly 10 kW to 25 kW). * **Physical weight**: Approximately 33,000 pounds. * **Footprint**: 1,900 square feet for the machine itself, plus an additional 1,000 square feet dedicated solely to air conditioning equipment.
[04:10](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=250s) The Minicomputer Revolution: The PDP-11/70
Moving into the 1970s, the minicomputer reshaped the computing landscape by decentralizing access. Cantrill points to Digital Equipment Corporation's (DEC) PDP-11/70 as the archetype of this generation. Unlike sprawling mainframes, the PDP-11/70 brought compute capability closer to local working groups and departments. Its cultural resonance endures: Cantrill notes that one of his co-founders keeps a working front-panel replica at home, powered by a Raspberry Pi driving the blinking lights.
The minicomputer wave dramatically shattered commercial forecasts. DEC originally anticipated building roughly 10,000 units of the PDP-11/70 family; instead, they shipped over 100,000 systems, cementing DEC's business and expanding the reach of Unix and multi-user operating systems across commercial and academic sites.
[05:51](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=351s) Big Iron in the Dot-Com Era: The Sun Enterprise 10000
Cantrill spent fourteen years at Sun Microsystems and introduces the Sun Enterprise 10000 (the "Starfire" or "E10K") as his personal generation's touchstone. Shipped in the late 1990s, the machine was an imposing monolithic server boasting up to 64 UltraSPARC CPUs and 64 GB of RAM, housed in a cabinet built to look imposing.
Cantrill warns younger engineers that the tech sector is not immune to economic downturns, reminiscing about the dot-com bubble when Starfire servers formed the backbone of the nascent commercial web. Companies often expanded by simply moving to larger single-node machines rather than refactoring their software for distributed resiliency. A notable casualty was eBay:
* eBay began on a simple dual-processor machine and scaled upward into a 64-processor Sun E10K. * Because the architecture failed to accommodate horizontal redundancy or scheduled maintenance windows, the single system became a single point of failure. * In 1997, eBay suffered a catastrophic outage lasting roughly 22 hours, exposing how brittle internet commerce was when anchored to individual monolithic machines:
> "It was eye-opening because of how important server-side computing had become that we were now actually running commerce on a single machine, running commerce with the server-side computers that we had actually not really designed with uptime in mind suddenly became very load-bearing with respect to this new economy."
[07:44](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=464s) The x86 Microprocessor Takeover and Architectural Compromise
By the early 2000s, the cost dynamics of microprocessors changed decisively. Established RISC processor architectures—including SPARC, IBM POWER, PA-RISC, and DEC Alpha—could no longer keep pace with the massive manufacturing and economic scale of Intel's commodity x86 chips. Customers found they could purchase commodity x86 hardware delivering comparable performance for a fraction of the cost, making large SMP servers uneconomical:
> "What people began to realize is like, actually I can get you this a 64-processor machine, but I can have a workload that runs maybe with a quarter of the number of CPUs... but I can do that for a 20th of the cost or 1/100th of the cost."
```mermaid flowchart TD accTitle: Evolution of Server Hardware Architectures accDescr: The shift from early vacuum-tube mainframes and minicomputers to massive RISC SMP boxes, followed by the takeover of PC-derived commodity x86 servers.
subgraph S1["Custom Large-Scale Platforms"] M1["IBM 709 (1961)<br/>Mainframe scale, CTSS, 205 kW"] M2["DEC PDP-11/70 (1970s)<br/>Minicomputer, local Unix compute"] M3["Sun Enterprise 10000 (1990s)<br/>64-way SMP RISC (SPARC)"] M1 --> M2 --> M3 end
subgraph S2["Commodity x86 Disruption"] PC["IBM PC Architecture (1979)<br/>Designed for hobbyists (Boca Raton)"] X86["Microprocessor Economics<br/>Intel x86 volume undercuts RISC"] SRV["HP ProLiant DL380 Gen5 (2009)<br/>Rack-mounted PC: CD tray, VGA, 8259 PIC"] PC --> SRV X86 --> SRV end
M3 -.->|"Extinguished by cost/performance"| SRV ```
This market dynamic produced a strange technical regression. Cantrill highlights the HP ProLiant DL380 (specifically a Gen5 model from roughly 2009) as the ubiquitous successor to the enterprise server. Despite its rack-mounted form factor, the system fundamentally remained a personal computer adapted for a server rack.
Cantrill points out the oddities embedded in a 2009 enterprise machine: * A physical CD-ROM drive on the front panel, useless inside a remote data center. * A legacy analog VGA display port. * The continued emulation of legacy PC chips dating back to the original 1981 IBM PC (designed in Boca Raton around 1979), such as the Intel 8259 Programmable Interrupt Controller (PIC).
The dominant processor line won the commodity market on sheer economics, but in doing so, it dragged along three decades of legacy PC baggage into the core of enterprise server infrastructure. At the same time, companies facing massive hyperscale demand began recognizing that standard commercial rack servers no longer met their needs.
[11:11](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=671s) The Cheap First Steps of Hyperscale: Google’s Velcro Era
By 2009, Google’s infrastructure needs had expanded dramatically, leading the company to the realization that deploying ordinary personal computers in data centers made little sense. Their first attempt at designing custom hardware was an infamous, stripped-down system built to minimize costs at all costs. Storage disks and the power supply were held down with Velcro. Instead of relying on a centralized uninterruptible power supply (UPS), Google attached an individual 12-volt battery directly to each server chassis. The motherboard was a rock-bottom consumer board from Gigabyte—the kind of component Bryan Cantrill jokes you could sweep off the floor—reflecting an effort to shave every single penny off machines bought in massive volume.
```mermaid flowchart TD accTitle: Tradeoffs of Early Hyperscale Cost Cutting accDescr: Diagram illustrating Google's early cost-cutting measures versus the resulting operational failures up the stack.
subgraph CostCutting["Cost-Cutting Measures"] D1["Velcro-mounted Disks & PSU"] D2["12V Battery per Server (No UPS)"] D3["Refurbished / Non-ECC DRAM"] D4["Rock-bottom Consumer Motherboards"] end
subgraph HiddenToll["The Hidden Operational Toll"] F1["Silent Memory Corruption"] F2["Unpredictable Machine Panics"] F3["High Cascading Stack Failures"] end
CostCutting -->|"Pennies saved up front"| HiddenToll ```
That aggressive skimping came with severe drawbacks. In trying to build the cheapest hardware possible, Google relearned an age-old lesson in systems engineering: penny-pinching on component quality extracts an immense operational toll. Refurbished memory and non-ECC DRAM led to corruptions and erratic failures across the software stack that far outweighed the pennies saved up front. As Cantrill emphasizes:
> “Google learned a lesson that has been learned for time immemorial in computing that is that you always want to seek value, but you have to be careful about unwittingly really getting what you paid for.”
Even so, both Google and Facebook were onto something essential: they were actively stripping out consumer ephemera that had no place in server infrastructure, eliminating optical CD drives, legacy VGA ports, and bulky consumer accoutrements in favor of purpose-built machines.
---
[13:22](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=802s) Rack-Level Efficiency: Facebook’s Tioga Pass and OCP Innovations
By the mid-2010s (roughly 2016–2017), hyperscalers had evolved far beyond makeshift motherboards to true rack-level co-design. A prime example is Facebook’s Open Compute Project (OCP) compute sled, Tioga Pass. In this architecture, individual compute sleds eliminate dedicated onboard power supplies entirely. Instead, each sled slides directly into a DC bus bar at the back of the chassis, powered by a centralized power shelf in the middle of the rack that handles all conversion from AC. Because every stage of power conversion bleeds energy as waste heat, eliminating conversion hops is vital for driving down Power Usage Effectiveness (PUE) and ensuring that electrical power goes toward compute rather than heating the data center floor.
```mermaid flowchart LR accTitle: Hyperscale Rack Integration accDescr: Flowchart illustrating the modular components feeding into Facebook's Open Compute Project rack architecture.
subgraph Sled["Tioga Pass Compute Sled"] TP1["Dual/Multi Socket Sled"] TP2["Front-Accessible Network Cables"] TP3["Direct DC Blind-Mate Connector"] end
subgraph RackSystem["OCP Rack-Scale Infrastructure"] PS["Centralized 12V DC Power Shelf"] BB["Integrated Bus Bar"] SW["Wedge Network Switch"] ST["Bryce Canyon Storage Chassis"] end
TP3 -->|"Direct connection"| BB PS -->|"Powers"| BB SW --- RackSystem ST --- RackSystem ```
The physical layout was rethought from scratch to optimize operations and servicing: - **No onboard power supplies:** Power conversion is consolidated into a dedicated, efficient shelf in the middle of the rack, mating directly with compute sleds via an integrated DC bus bar. - **Front-accessible cabling:** Network cables and interconnects are placed at the front of the chassis, allowing technicians to service sleds without navigating hot aisles. - **Wider chassis geometry:** Rejecting the historical, arbitrary 19-inch rack form factor, the Open Rack standard fits over standard 24-inch floor tiles while accommodating a wider, taller envelope holding three sleds across instead of two. - **Cohesive open ecosystem:** Sleds integrate into an open portfolio featuring Facebook’s custom network switch (Wedge) and high-density storage enclosure (Bryce Canyon).
---
[15:34](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=934s) The Enterprise Stagnation: Personal Computers in Disguise
While hyperscalers built streamlined, rack-scale hardware, mainstream enterprise and server-side hardware barely progressed. Comparing a 2009 commercial server to a 2020 commercial server from vendors like HP shows that little fundamentally evolved: the CD drive was replaced by a DVD drive, and the VGA port was replaced by an HDMI port. These are incremental upgrades suited for a desktop computer running Microsoft Windows in an office, not an enterprise server engineered for a modern elastic data center. Enterprise servers remain rack-mounted personal computers.
Cantrill recounts his career path—spending 14 years at Sun Microsystems until Sun was “invaded” (acquired by Oracle), after which he departed to spend a decade at cloud provider Joyent (subsequently acquired by Samsung). Building out a large private cloud on standard commercial enterprise hardware proved profoundly frustrating. It was not merely an aesthetic grievance; running desktop architectures in enterprise racks introduces crippling operational failures up and down the stack. For organizations lacking the scale and “infrastructure privilege” of Google or Facebook, observing open-source hyperscale breakthroughs that remain inaccessible off-the-shelf only sharpens the frustration.
> “It sharpens the pain for those of us who don't have the infrastructure privilege of these folks to know that like actually there's great innovations, we just can't have them, and that's that's very frustrating.”
---
[17:20](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1040s) The Hardware-Software Divide and the Silenced DIMM Pandemic
Against the prevailing industry assumption that public cloud monopolies will swallow all computing, Cantrill defends a contrary position: ownership of physical hardware remains essential. Organizations choose to operate their own infrastructure for risk mitigation, control, and above all, compelling economic reasons—at scale, owning compute is far cheaper than renting it indefinitely from Amazon Web Services or other cloud giants.
However, companies attempting to build on-premises infrastructure face a persistent architectural standoff:
| Layer | Primary Stakeholder | Fundamental Constraint | |:--- |:--- |:--- | | **Hardware Layer** | Traditional Server OEMs (HP, Dell) | Trapped designing systems to look like generic PCs to boot Windows; zero ownership or visibility into cloud software stacks. | | **Software Layer** | Hypervisors / Operating Systems | Software maintainers lack control over underlying hardware logic and proprietary firmware implementations. | | **Open Source Stack** | DIY Enterprise Operators | Forced to cobble together disparate packages and consumer-rooted machines never designed for cloud orchestration. |
This divide causes real operational damage, exemplified by a severe DIMM failure pandemic Cantrill experienced in production. Nodes were continually hit by uncorrectable memory errors that instantly panicked systems without warning. In standard ECC memory, uncorrectable double-bit errors rarely strike out of nowhere; they are almost invariably preceded by an escalating pattern of correctable single-bit errors caused by design defects, heat, or poor DIMM calibration.
The investigation revealed that proprietary vendor firmware was silently intercepting and discarding all correctable error events instead of logging them upward. Because the operating system never received telemetry about the rising correctable error counts, the software could not proactively alert operators, isolate degrading nodes, or trigger memory retraining routines before an uncorrectable crash brought down the server:
> “The uncorrectable that would ultimately panic the box, and if you've been around memory for any length of time you know that's not really the way the world works, that you don't in ECC memory you don't see an uncorrectable generally out of clear blue sky. You generally see a rising number of correctable errors, and those correctable errors indicate you've got a problem here.”
[21:07](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1267s) The Clean Sheet Approach: Keeping the Microprocessor, Rebuilding Firmware
Bryan Cantrill recalls the exasperating struggle of trying to get PC-oriented hardware vendors to elevate hardware errors cleanly into operating system software, comparing the bureaucratic friction to “trying to get a bill through Congress.” When you approach a personal computer vendor asking for a custom firmware build tailored to hyperscale infrastructure, they react with utter bewilderment: “Why would anyone running a personal computer want their own firmware? It doesn't make any sense.” The fundamental disconnect is that cloud operators are not running personal computers; they are running a cloud. Because this disconnect has been felt acutely across the entire computing industry, Cantrill argues that incremental fixes are insufficient: it is time to take a clean sheet of paper and redesign the computer from scratch for the year 2020.
Starting from scratch, however, does not mean reinventing everything. Cantrill emphasizes that they have no interest in redesigning the core microprocessor itself. Modern microprocessors from Intel, AMD, or ARM are exceptionally sophisticated and fully fit for enterprise purposes. The true structural problems lie in the firmware ecosystem surrounding those processors. In traditional commercial servers, operators run machines with zero knowledge of the actual firmware binaries executing underneath them. Applying a standard vendor BIOS update means flashing an untrusted black box. Performing even rudimentary binary inspection on these vendor ROMs reveals terrifying anomalies, such as embedded web URLs in the lowest-level machine initialization code: “This is the brainstem of my data center. Why is there a URL in here?” When you attempt to ask vendors why their firmware contains URLs, you find that nobody can answer the question.
```mermaid flowchart LR accTitle: "Clean Sheet Redesign Scope" accDescr: "Separating components to keep versus components to overhaul in the 2020 clean-sheet redesign."
subgraph Keep["Keep As-Is"] CPU["Microprocessors<br/>(Intel / AMD / ARM)"] end
subgraph Overhaul["Complete Overhaul"] direction TB FW["Firmware & Attestation"] SP["Service Processor Architecture"] RS["Rack-Scale Integration"] end
Keep -.->|"Hosts Fit-for-Purpose Compute"| Overhaul ```
- Bryan Cantrill: “This disconnect was felt very acutely by us certainly, and it's been acutely felt by many, many, many people; this is not novel or not unique to us, so we feel you really need a fundamentally new approach.” - Bryan Cantrill: “Why is there a URL in here? You'll try to get an answer to that question; it's not that it's like an uncomfortable question, it's you literally can't find anyone who can answer it.”
---
[23:25](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1405s) The Supply Chain, American Megatrends, and the BMC Attack Surface
The opacity of server firmware creates deep security and provenance vulnerabilities. Even hardware vendors that profess a desire to open-source their firmware are often incapable of doing so because the firmware is not actually theirs. It is licensed from third parties whose legacy roots stretch back to the early PC era. Cantrill expresses genuine disbelief that American Megatrends Inc. (AMI) still runs the fundamental infrastructure of the internet: “How is AMI still running at the brainstem of humanity?” Because these third parties refuse to share their proprietary source code, customers cannot inspect, verify, or attest the software executing on their servers.
This vulnerability became glaringly apparent during the public reaction to the fall 2018 *Bloomberg* report alleging hardware supply chain infiltration at Supermicro. While Cantrill notes that the story as written was almost certainly factually incorrect—and no physical spy-chip hardware was ever produced—he points out the absurdity of suspecting an elaborate physical interdiction campaign when servers are already wide open at the software layer: “Why would anyone mount this very sophisticated attack frankly when you can just walk in through the firmware?” Most Supermicro Baseboard Management Controllers (BMCs) ship with factory default root credentials, remain directly exposed to the public internet, and suffer from severe vulnerabilities. Cantrill points to research by Rick Altherr presented at the Open Source Firmware Conference, where Altherr uncovered the "USB Anywhere" vulnerability and identified 77,000 publicly exposed BMCs that could have been completely compromised over the network.
The root of this systemic risk is the BMC itself—a secondary computer running inside the host server. Far from being a simple controller, a typical BMC is an Aspeed or Nuvoton System-on-Chip (SoC) running U-Boot, Linux, and opaque proprietary software stacks. Critically, the BMC acts as a master on the host server's PCIe bus while simultaneously maintaining direct external network interfaces. Leaving an unvetted, proprietary operating system wired directly between the wild internet and the machine's memory bus represents an untenable security architecture.
- Bryan Cantrill: “How is AMI still running at the brainstem of humanity? American Megatrends Incorporated, this is a company that was around when I was a kid—I'm old—it has, I mean again it's got a right to exist, but why does an AMI BIOS exist on industrial-grade machines? It makes no sense.” - Bryan Cantrill: “Why would anyone mount this very sophisticated attack frankly when you can just walk in through the firmware?”
---
[26:19](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1579s) Tearing Down the BMC and Killing the DOS Mentality in Host Firmware
To restore server integrity, Cantrill argues that the entire concept of the modern BMC must be dismantled and returned to a lean, purpose-built service processor backed by a true hardware root of trust that attests all firmware. A service processor should focus strictly on fundamental physical maintenance: power-cycling the host ("bouncing the box"), providing a serial console, and driving basic chassis thermal and fan controls. It has no business hosting virtual VGA display adapters, virtual USB stacks, or bloated internet-facing software layers.
```mermaid flowchart TD accTitle: "Service Processor vs Host Lifecycle Separation" accDescr: "Comparing the lean duties of an attested service processor with the ephemeral lifecycle of host firmware handing off to the OS."
subgraph SP["Attested Service Processor"] direction TB B1["Power Cycling ('Bounce the Box')"] B2["Serial Line Interface"] B3["Thermal & Fan Control"] end
subgraph Host["Clean Host Firmware Lifecycle"] direction TB H1["Hardware Initialization"] H2["Attestation & Handoff"] H3["Exit Memory Completely"] H1 --> H2 --> H3 end
SP -.->|"Out-of-Band Control"| Host H3 ==>|"Clean Slate Execution"| OS["Host Operating System"] ```
Host boot firmware requires an equally radical philosophical purge. In Cantrill’s view, host firmware exists for a single, transient purpose: initialize the hardware, hand the execution thread cleanly to the host operating system, and vanish from memory. Cantrill forcefully rejects the lingering "DOS mentality" of modern firmware architectures like System Management Mode (SMM) and ACPI runtime calls, where unseen vendor code remains resident indefinitely to execute arbitrary logic behind the operating system's back. Recalling his childhood frustrations of growing up using DOS without memory protection in the 1980s—wrongly assuming that computers were simply destined to crash and reboot at random until he discovered Unix in college—Cantrill insists that modern cloud servers should never rely on load-bearing, hidden firmware executing in stealth.
Compounding this problem are the secondary internal co-processors, such as the Intel Management Engine (ME) and the AMD Platform Security Processor (PSP). Intel's ME is an entirely independent microcontroller on the motherboard running an operating system based on MINIX with total dominion over system buses and hardware state, subject to proprietary vulnerabilities. While AMD's PSP at least lives directly on the processor die, it remains an opaque black box. Cantrill asserts that understanding every single instruction executing on the physical silicon is a completely reasonable and fundamental demand for modern enterprise computing.
- Bryan Cantrill: “Your job is to bring the host operating system its cup of coffee and shoot yourself in the head; that should be the role of host firmware.” - Bryan Cantrill: “This idea that firmware should execute and then somehow stay resident so it can be called into at arbitrary times to do arbitrary things is—this is DOS, that's that DOS mentality and approach, and DOS robbed me of my childhood.” - Bryan Cantrill: “Visibility into it is a reasonable thing: to be able to understand every instruction that's executing on your computer, that is a reasonable request.”
---
[29:22](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1762s) True Rack-Scale Co-Design
Beyond internal motherboard architecture, rethinking the computer requires treating the entire rack as the atomic unit of compute. Cantrill points out that simply stacking twenty standard 2U commodity servers into an enclosure and lashing them together with patch cables does not constitute a rack-scale design; it is merely “rack and stack.” A true rack-scale architecture demands tight, unified co-design between the top-of-rack (ToR) network switch, internal storage pools, and compute blades, making every layer deeply aware of the others.
This vision cannot be executed purely in hardware; it fundamentally requires unified system software. Cantrill points out that earlier industry initiatives—such as Intel’s Rack Scale Design (RSD)—consistently failed to deliver because hardware companies historically treated software as “someone else's job.” Without an integrated software operating substrate, rack-level hardware features cannot be coordinated. Furthermore, realizing this design requires shifting the boundaries of interoperability. While enterprise hardware buyers often treat universal switch interoperability as a sacred virtue, unconstrained interoperability acts as an enemy to tightly optimized systems engineering: “Interoperability is great in principle, but it is very corrosive when you want to make an actual tight integrated design.” Instead of forcing internal server trays to negotiate with arbitrary third-party ToR switches, the ToR switch must be pulled inside the system boundary, pushing external network interoperability out to the rack’s exterior boundary while maximizing chassis density and performance within.
- Bryan Cantrill: “By rack-scale design, I mean really thinking about the entire rack; taking a bunch of 2Us and slapping it into a rack is not a rack-scale design, that is just rack and stack.” - Bryan Cantrill: “Interoperability is great in principle, but it is very corrosive when you want to make an actual tight integrated design.”
[30:48](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1848s) The Power Reality of Mainstream Enterprises and Bus Bar Architecture
Hyperscalers operate in a world detached from standard enterprise constraints: they design data centers from scratch, locating facilities beside dams and running up to 25 kW per rack. Bryan Cantrill points out that while packing 25 kW into a rack sounds fantastic, it is completely impractical for mainstream enterprises. The power draw and cooling demands are simply too immense, leaving enterprise data centers constrained to a realistic power envelope of roughly 10 to 15 kW per rack.
Within that 10 to 15 kW budget, however, systems must achieve maximal compute density and adopt more efficient delivery mechanisms, such as bus bar-based power design. Cantrill expresses utter disbelief that major enterprises with massive computational footprints are completely locked out of this architecture:
> “Why can I not buy a machine if I'm, you know, General Electric, or I'm Barclays, if I am General Motors, I can't buy a bus bar-based machine, no matter how much compute I'm operating?”
He argues that it is ridiculous for mainstream infrastructure to ignore these efficiencies. High-power density does not mean low-power computing; rather, it demands relentlessly efficient operation from the hardware up.
- Hyperscaler data centers: Custom-built near major power sources (such as hydroelectric dams), drawing 25 kW per rack. - Mainstream enterprise envelope: Constrained to approximately 10 to 15 kW per rack due to practical power and cooling limits. - The bus bar gap: Despite running massive scale, large enterprises (GE, Barclays, GM) are barred from purchasing rack-level bus bar designs off the shelf.
---
[32:15](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1935s) Co-Designing Hardware and Software: The 2020 Computer Boundary
Cantrill attributes his perspective to his deep roots at Sun Microsystems, remarking that you simply cannot get the Sun out of him. He is convinced that true system quality comes only from the tight co-design of hardware and software. When both halves are designed together, engineers gain complete control over system elements, resulting in a significantly higher-performing, coherent artifact.
The definition of a computer has fundamentally shifted. In the 1970s and 1980s, the boundary of the computer lived at the multi-user shell. By 2020, that boundary has migrated all the way up the stack:
> “I think in terms of in 2020 the boundary for the computer is at the API endpoint to provision a virtual machine.”
Between that API endpoint and the bare metal lies an enormous software surface: operator and developer APIs, compute control planes, storage control planes, the top-of-rack (ToR) switch software, and the hypervisor. Cantrill laments that the modern industry forces end users to cobble all these pieces together themselves, calling the situation profoundly unfair and unjust.
```mermaid flowchart TD accTitle: The Modern Computer Stack Boundary accDescr: Diagram illustrating the modern boundary of a computer at the API provisioning layer down through the hardware substrate.
subgraph API_Layer ["Modern Computer Boundary"] API["Operator & Developer API Endpoints<br/>(VM Provisioning Boundary)"] end
subgraph Control_Planes ["Integrated Infrastructure Software"] CCP["Compute Control Plane"] SCP["Storage Control Plane"] TOR["Top-of-Rack (ToR) Switch Software"] HYP["Hypervisor"] end
subgraph Hardware_Substrate ["Co-Designed Physical Substrate"] HW["Rack-Scale Hardware<br/>(Bus Bar Power, Servers, Network)"] end
API --> CCP API --> SCP CCP --> HYP SCP --> HW TOR --> HW HYP --> HW ```
---
[33:49](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=2029s) Open Infrastructure and the Case for Attainability
While Cantrill advocates for delivering an integrated machine where the software is tightly welded to the hardware, he draws a sharp line against proprietary lock-in. The era of proprietary infrastructure software is dead, and enterprise servers cannot follow Apple's iPhone model. The iPhone offers a beloved user experience, but its complete inaccessibility makes it impossible to inspect, understand, or modify the underlying system. Instead, rack-scale system software must be built on the open-source tradition, fully open and rigorously attested.
Addressing the skepticism of those who treat server architecture stagnation as an intractable status quo, Cantrill admits that he was once among them: frustrated by the bifurcated world between hyperscalers and the enterprise, yet hoping things would magically improve. Upon deploying new hardware and realizing things had actually worsened due to deep structural dysfunction, he concluded that passivity was no longer viable:
> “We have to be able to do this, we have to solve this problem, because, one, this is not science, right? This is engineering.”
This problem is fully solvable because a purpose-built rack does not need to run every legacy operating system from MS-DOS 6.22 to modern obscure variants. Hyperscalers never run arbitrary bare-metal operating systems; they run their own hypervisors. By targeting specific hypervisors and a curated set of devices, engineers eliminate false generalities in both software and hardware, reducing a seemingly sprawling problem into a bounded, tractable engineering effort.
- Anti-pattern: The closed-box iPhone model that prevents user inspection and low-level system modifications. - Prerequisite: Fully open-source, fully attested infrastructure software stack. - Scoping advantage: Tightly tailoring bare-metal firmware and hypervisors eliminates decades of legacy operating system compatibility overhead.
---
[36:50](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=2210s) The Spectre/Meltdown Wake-Up Call and Hardware Roots of Trust
A major catalyst enabling this architectural shift was the catastrophic security revelations of 2018. Cantrill recalls discovering Spectre and Meltdown on January 1, 2018, reading a speculative Hacker News thread about suspicious Linux patches alongside the rest of the world. Despite running huge fleets of Intel processors, his team had received no embargo warning. As the details unfolded over subsequent days, the full horror of Meltdown set in.
The great irony of Meltdown and Spectre was that speculative execution was the exact architectural breakthrough that had originally enabled x86 to break through the memory wall and crush competitive microprocessors. Cantrill notes a conversation with Jon Masters regarding whether the SPARC architecture would suffer from similar vulnerabilities:
> “I was talking even John Masters, who was saying that like, ‘Hey, do you think SPARC would have any of these issues?’ Like, no, SPARC would not have any of these issues, because SPARC's problem was not speculative enough.”
These microarchitectural vulnerabilities acted as a beacon to security researchers eager for notoriety, unleashing intense scrutiny upon previously unexamined, ill-conceived firmware deep within the stack. This reckoning sparked an industry-wide scramble for hardware roots of trust and firmware attestation. Cantrill points to Microsoft's Project Cerberus and Google's Titan family as key milestones. In fact, Cantrill highlights the Google Chromebook as one of the best, most underappreciated computers built, precisely because it solved firmware attestation and hardware root of trust on client machines. Unlike the iPhone, a Chromebook permits users to flash custom firmware; however, its hardware root of trust ensures the system explicitly detects and acknowledges that it is running non-native firmware, refusing to blindly attest that its underlying software substrate can be trusted. This lineage has now progressed toward broader industry efforts such as Google's OpenTitan project.
[40:42](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=2442s) The Open EDA Movement, HDLs, and Bluespec
Bryan Cantrill draws an analogy between what is happening in modern hardware development and the container world, framing new open infrastructure initiatives as akin to a "Kubernetes versus Borg" moment. Joining forces with these broader collaborative efforts means a new startup is no longer stranded trying to reinvent every wheel from scratch. A parallel, yet underappreciated, revolution is taking place in electronic design automation (EDA). Pointing out the historical paradox of hardware development, Cantrill observes: “It was easier to get a hardware company funded two decades ago, but hardware has never been easier than it is today.”
```mermaid flowchart LR accTitle: Modern Open-Source Hardware Development Stack accDescr: Progression from higher abstraction design down through HDLs and synthesis to FPGA soft cores.
subgraph Design ["Design & HDL"] direction TB BS["Bluespec (High-level Abstraction)"] HDLs["Chisel / SpinalHDL / Verilog"] end
subgraph Toolchain ["Open Toolchain"] direction TB Yosys["Yosys Synthesis"] Verif["Open Verification Engines"] end
subgraph Target ["Silicon Target"] FPGA["FPGA Substrate"] RiscV["License-Free RISC-V Soft Core"] end
Design --> Toolchain Toolchain --> Target FPGA -.->|"instantiates"| RiscV ```
EDA software historically served as one of the last bastions of completely proprietary, locked-down software. Today, that fortress is giving way to open tools and expressive hardware description languages like Yosys, Chisel, and SpinalHDL, alongside open verification frameworks. Most notably, Bluespec—originally invented more than fifteen years prior at MIT—was released as open source only days before the seminar. Calling it merely an HDL does it a disservice, Cantrill argues, because it elevates the level of abstraction at which designers define FPGA behavior. That newfound accessibility radically lowers the barrier for engineers to roll their own custom FPGAs.
- Yosys provides modern open-source synthesis, pairing with newer hardware construction languages like Chisel and SpinalHDL. - Bluespec open-sourced its compiler and language roughly ten to fourteen days prior to this talk, providing a higher-level semantic model for FPGA logic design. - The barrier to designing, simulating, and deploying custom FPGA hardware has cratered compared to the proprietary toolchains that dominated two decades ago.
---
[42:24](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=2544s) The Rise of RISC-V: Clean Architecture and Free Soft Cores
Cantrill highlights the RISC-V instruction set architecture, spearheaded by David Patterson and his colleagues at UC Berkeley, as another foundational piece of the modern hardware puzzle. He enthusiastically recommends the *RISC-V Reader* (referring to the instruction set atlas), describing it as a delightful read because of the sheer intentionality behind the specification. Instead of piling on historical baggage, the designers systematically cataloged decades of processor architectural successes and failures, deliberately extracting the good ideas while discarding flawed architectural conventions.
Beyond the clean architecture, RISC-V’s decisive advantage is legal and economic: it is entirely open and royalty-free. Anyone can drop a license-free soft core onto an FPGA without paying IP fees or signing restrictive non-disclosure agreements:
> “And you can now have your own software running on that RISC-V core. Now is that software running with megabytes and megabytes of memory? No, it's running in a pretty constrained environment, but it allows you to actually have computational programmability at very, very, very low levels of the stack, i.e., in the FPGA.”
- RISC-V avoids the historical pitfalls of earlier instruction set architectures by conducting a deliberate post-mortem on decades of computer engineering. - Royalty-free implementations allow designers to spin up embedded soft cores in an FPGA fabric cheaply and quickly. - These soft cores afford developers full computational programmability in micro-environments deep inside server subsystems, even where memory is counted in kilobytes rather than megabytes.
---
[44:05](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=2645s) Open Firmware and the Open Compute Project (OCP)
For years, open firmware appeared to be a hopeless crusade, leaving servers condemned to proprietary legacy BIOS and opaque vendor blobs forever. However, Cantrill explains that hardware security debacles like Spectre and Meltdown shattered that inertia by laying bare the catastrophic danger of vulnerabilities lurking deep in the low-level silicon stack. Hyperscalers, unwilling to tolerate black-box firmware they could neither audit nor remediate, began demanding transparency from microprocessor vendors and directly funding open firmware efforts. Reflecting on this turning point, Cantrill says: “There was a time when I felt like open firmware was never going to happen—that is to say we would have a closed legacy BIOS forever. But with Spectre and Meltdown, and with the new focus on these vulnerabilities deep in the stack, and thanks to the hyperscalers who really demand this and are funding it accordingly... we are now seeing the arrival of open firmware.”
```mermaid flowchart TD accTitle: Drivers of the Open Firmware Transition accDescr: Security crises and hyperscaler leverage pushing the transition away from closed legacy BIOS to open firmware and OCP.
subgraph Catalysts ["Industry Catalysts"] SM["Spectre & Meltdown Vulnerabilities"] Hyper["Hyperscalers (Google, Meta/Facebook)"] end
subgraph Forum ["Collaboration Hubs"] OCP["Open Compute Project (OCP)"] OSFC["Open Source Firmware Conference"] end
subgraph Outcome ["Modern Open Stack"] FW["Auditable Open Firmware (Coreboot, LinuxBoot)"] Spec["Open Server Reference Hardware (e.g., Tioga Pass)"] end
SM -->|"forces transparency"| Hyper Hyper -->|"funds & demands"| OCP Hyper -->|"supports"| OSFC OCP --> Spec OSFC --> FW ```
Cantrill recalls attending the Open Source Firmware Conference (OSFC) hosted at Google and Facebook, describing it as the single best conference he had attended in the previous year. It evoked the nostalgic feeling of early tech gatherings from before the ubiquitous internet era, where engineers who assumed they were the only people on earth obsessing over an obscure discipline stepped into a room to discover hundreds of kindred spirits. Much of this momentum is driven through the Open Compute Project (OCP). Facebook established OCP around 2010–2011 to share power-efficiency innovations, like centralized DC busbar architectures and designs such as the Tioga Pass motherboard. While the notion of Facebook acting out of a heartfelt sense of “social responsibility” feels surreal in hindsight, the project quietly blossomed into an indispensable, transparent forum where competing hyperscalers share real-world data center hardware designs.
- Spectre and Meltdown forced hyperscalers to realize that black-box firmware represents an existential security risk. - The Open Source Firmware Conference (OSFC) has united a thriving developer community dedicated to dismantling legacy proprietary firmware blobs. - OCP originated from Facebook engineers seeking to standardize power distribution and server mechanics, growing into the primary venue where production hardware architectures are publicly disclosed.
---
[47:24](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=2844s) The System Software Shift: Databases, Consensus, and Languages
The system software landscape has transformed just as radically as hardware. Open source has evolved from an alternative paradigm into the baseline expectation for data center infrastructure. While venture-backed open-source companies now grapple with identity crises over commercialization and monetization, the operational ecosystem has matured enormously. Production-ready, resilient software runs open in data centers at massive scale, demonstrating stability that was unthinkable ten years prior.
| Era | Consensus Systems | Database Architectures | System Software Landscape | |:--- |:--- |:--- |:--- | | **c. 2010** | Apache ZooKeeper (finicky, complex, painful to operate) | Proprietary relational engines still dominant; nascent open-source options | Closed Unix/Windows kernels lingered; low-level firmware closed source | | **c. 2020** | Modern Raft-based systems, distributed key-value consensus engines | Open-source distributed databases run at planetary scale; proprietary engines declining | Open-source Linux/illumos kernels standard; emergence of Rust and open firmware |
A decade ago, distributed consensus was practically synonymous with Apache ZooKeeper. As Cantrill remarks, “ZooKeeper is not fun—even if you love ZooKeeper, you will acknowledge that it is not fun.” By 2020, battle-tested distributed databases and consensus mechanisms became ubiquitous off-the-shelf primitives. Operating systems are now almost universally open source, with proprietary databases similarly on the verge of obsolescence.
Yet the most staggering transformation was one Cantrill never would have anticipated: an architectural leap forward in systems programming languages. As an unapologetic, pragmatic systems hacker, he had historically treated programming languages merely as tools, looking back wryly on his own youthful fascination with features like operator overloading:
> “I think my past self would have tried to take a swing at my future self, because I'm a systems person... I view programming languages as part of getting a job done, very pragmatically. And yes, I went through, you know, a youthful phase of operator overloading and so on, but you grow out of that... because you'll realize that some of the neat things you can do in languages doesn't mean you should do them, certainly not in deployed systems. And especially debugging the code of others will help a great deal in this regard—if you're wondering how I can actually help accelerate this process, go debug the code of others.”
Having lived through the scars inflicted by MS-DOS in his youth and spent decades untangling complex C++, Cantrill sets the stage for why modern type safety and memory-safe systems languages are finally rewriting the rules of the trade.
[50:32](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3032s) The Fatal Flaws of Garbage Collection and the Rejection of C++
Reflecting on past language choices, Bryan Cantrill recalls having his young adulthood consumed by C++, leading to an intense love affair that ultimately ended in a vow never to return. While modern garbage-collected languages like Go and Java have their place, he insists that garbage collection has no business in low-level systems programming. Cantrill makes clear that he is not speaking pejoratively about garbage collection as a whole—recognizing its utility for the vast majority of software worldwide—but argues that the systems he builds require strict determinism. In systems programming, one cannot tolerate an unseen, unheard whistle being blown that halts the software so a runtime can scurry around doing uncontrolled work behind the scenes.
```mermaid flowchart TD accTitle: The Problem with Garbage Collection Under Load accDescr: Flowchart illustrating how garbage collection degrades under heavy workloads into an uncontrollable heap scanner.
subgraph Normal["Normal Conditions"] A["Small Heap Footprint"] --> B["Predictable Latency"] end
subgraph Surge["High Workload / Heavy Traffic"] C["Surging Workload"] --> D["Large, Fully Legitimate Heap"] D --> E["GC Becomes a Periodic Heap Scanner"] E --> F["Stop-the-World Latency Spikes"] end ```
The fundamental failure mode of garbage collection is that it works fine on sunny days, but degrades catastrophically on stormy ones. When a system is under heavy load, its legitimate, active heap swells with real work. If an engineer has built a meticulously manicured system where allocated memory is actually in active use rather than discarded garbage, the garbage collector degenerates into an unprompted, periodic heap scanner over which the engineer has zero control. Because of this unpredictability, Cantrill resolved years ago that garbage collection was simply incompatible with the systems he creates, resigning himself to the idea that he would write C for the rest of his career.
- Cantrill summarizes his systems philosophy: “I don't want garbage collection anywhere near the systems that I'm developing.” - Under heavy load, an efficient program with little actual garbage causes the collector to run periodic, expensive scans across a massive active heap. - Cantrill compares his acceptance of C to being a craftsperson who values knowing the exact physical reality beneath his code: “When you write C, you can feel the assembly underneath you.”
---
[52:47](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3167s) C, Undefined Behavior, and Vulnerabilities in DTrace
Although critics often disparage C as mere portable assembly, Cantrill views that low-level transparency as the exact quality a systems programmer demands to control the machine. However, the modern revolution in programming languages brought about by Rust has fundamentally changed his perspective. While C's lack of safety is notorious—likened to constantly playing with loaded weapons—the deeper systemic issue with C is composability. It is rarely the code written by an individual programmer that introduces disaster; rather, it is the inability to safely link against external libraries because C composes exceptionally poorly.
Even skilled engineers who believe they write correct C are working on shaky ground because the C standard is riddled with undefined behavior. Cantrill illustrates this vulnerability through personal experience with DTrace, a ubiquitous dynamic tracing system he co-authored around 2005. Over fifteen years of widespread deployment, DTrace suffered only a tiny handful of vulnerabilities, yet the two vulnerabilities Cantrill personally introduced were both caused by malicious integer overflow. In both cases, bounds checks that were completely correct for benign operating conditions failed when confronted with crafted malicious inputs, opening the door to arbitrary memory reads and privilege escalation. This painful lesson demonstrated that systems require more than just memory safety; they require integer safety as well.
- Cantrill emphasizes the historic importance of Rust: “I fervently believe that Rust is every bit as important revolution as C.” - In C, subtle integer arithmetic flaws bypass normal bounds checks: “The two vulnerabilities that I introduced were both due to effectively malicious integer overflow where I was doing a—I was comparing a bounds incorrectly.” - Unlike C, Rust's strict static model eliminates undefined behavior by enforcing rigorous memory ownership contracts and built-in protections against integer overflow.
---
[55:28](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3328s) Learning Rust, the Bargaining Phase, and the 35% Speedup
Rust shifts the cognitive burden of memory safety entirely to compile time through its strict ownership model. By tracking owners and lifetimes statically, the Rust compiler can guarantee memory safety and generate fast native binaries without requiring a runtime garbage collector. However, Cantrill warns that dabbling casually in Rust will punish newcomers: while an experienced C programmer can eventually develop an intuition for the compiler’s strictness by visualizing the underlying memory, the learning curve is notoriously steep and filled with frustration. Cantrill jokes that learning Rust forces a programmer through the five stages of grief until they find themselves bargaining with the compiler just to get code to build.
```mermaid flowchart LR accTitle: The C vs Rust Performance Surprise accDescr: Flowchart contrasting Cantrill's optimized C code with his naive Rust implementation utilizing standard B-trees.
subgraph C_Impl["Hand-Tuned C Implementation"] C1["Balanced Binary Tree"] --> C2["Manual Pointer Swapping"] C2 --> C3["Baseline Performance"] end
subgraph Rust_Impl["Naive Rust Implementation"] R1["Rust Standard BTreeMap"] --> R2["Memory Relocation & Cache Locality"] R2 --> R3["35% Faster Than Hand-Tuned C"] end ```
To test Rust on a small project, Cantrill initially tried writing a clever implementation, but soon realized he was not clever enough to fight the borrow checker. He abandoned cleverness and rewrote the software in the dumbest, most straightforward way possible just to achieve a clean compilation. Having previously authored an optimized version of the same program in C, he hoped the naive Rust code would land within 20% of his C performance. When he ran the benchmark, the Rust implementation was actually 35% faster than his hand-tuned C. The discovery triggered mixed emotions, feeling like a parent being soundly beaten at basketball by their own child: proud of the result, but deeply annoyed that his handcrafted C had been humbled.
- Cantrill notes the steep learning curve: “If you haven't waded into Rust, you definitely want to sit down and learn it; if you try to dabble with it, it will punish you because the—the model is different.” - Comparing the mental models of languages, Cantrill observes: “With C you could feel the underlying assembly; with Rust you can feel the underlying C.” - Upon measuring the benchmark results against his carefully written C implementation: “I ran it, and it was like 35% faster than my C.”
---
[58:06](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3486s) Why Rust Outperformed C: The Power of Safe B-Trees
Perplexed by why the Rust binary outperformed well-crafted C, Cantrill investigated the memory access patterns and contacted Rust core team member Steve Klabnik. Cantrill assumed that the Rust compiler must have achieved a groundbreaking breakthrough in solving the notorious memory disambiguation problem. To his surprise, Klabnik informed him that while LLVM and Rust could theoretically perform such exotic optimizations, none of them had actually been implemented yet. The speedup was not the result of compiler magic, but rather the intrinsic data structures mandated by Rust's design.
In Rust, the standard ordered associative collection is a B-tree (`BTreeMap`), rather than the balanced binary trees (such as red-black trees) ubiquitous in C. A B-tree offers dramatically better cache locality and algorithmic performance, but implementing one in C—especially as a reusable, general-purpose library—is extraordinarily difficult. Because balancing a B-tree involves physically copying and relocating elements in memory rather than merely swapping pointers, a C library would require an intricate, explicit ownership contract with its caller to avoid memory corruption, something C's type system cannot safely express. Because Rust encodes ownership and borrowing into the type system, safe and highly efficient B-tree implementations are straightforward to consume. Cantrill concludes that Rust forces developers into superior, high-performing architectural choices that would be nearly impossible to manage safely in C.
- Cantrill recalls asking Steve Klabnik about the performance disparity: “Steve, you know, it's amazing that the optimizations that you've pulled, and clearly that compiler knows so much about heaven and earth that it is able to truly solve the memory disambiguation problem.” - Klabnik's blunt response dismantled that theory: “No, it's—it's true that that's all possible; we haven't done any of that yet.” - Cantrill challenges developers to verify the difficulty of building robust, relocating data structures in unsafe languages: “There are not really good B-tree libraries in C—I mean, like take me up on this challenge, go look for a good B-tree library in C; it is really, really, really hard to implement.”
[01:00:07](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3607s) Rust’s Small Footprint and Embedded Systems
Bryan Cantrill discusses the extraordinary ability of the Rust programming language to compile down into tiny memory footprints without forfeiting expressiveness. On embedded soft-core RISC-V targets instantiated on an FPGA, available RAM might be limited to around 512 KB. Reflecting on a conversation with an embedded systems colleague, Cantrill jokes about the famous quote apocryphally attributed to Bill Gates that 640 KB ought to be enough for anybody:
> “640K is actually a lot of memory, it actually is, and you actually can do a lot with 640K, especially if you are careful about the way you spend it, and Rust allows you to slim things way, way down—borderline beyond what you can do with C.”
While C can yield extremely compact binaries, Rust achieves parity in minimal footprint while retaining rich, modern software abstractions. Cantrill highlights this as an exciting breakthrough for systems programming. In fact, the name of Oxide Computer Company is an explicit tip of the hat to Rust. He notes that the team has drawn deep inspiration from embedded systems like Tock OS—an open-source, embedded Rust operating system developed by Amit Levy, Phil Levis, and others at Stanford and partnering institutions.
[01:01:45](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3705s) Founding Oxide Computer Company and the Graveyard Slide Deck
Piecing together these advancements in open firmware, RISC-V, and Rust, Cantrill and his co-founders realized a commercial rack-scale server was finally buildable. They founded Oxide Computer Company and closed their seed funding round at the end of 2019. Raising seed capital for a hard-tech hardware venture was simultaneously frustrating and energizing, depending on whether investors grasped the thesis. By early 2020, Oxide had grown to a 15-person team, targeting a functional prototype by 2021 and production shipping systems by 2022.
To address the high failure rate among historical server startups, Cantrill prepared an extensive appendix for investor pitches, maintaining dedicated slides on virtually every failed computer company from the preceding 15 years:
> “When we were doing our raise, we I really wanted to learn from every single person's experience, and as a result I had an appendix slide on every single company you could possibly name that looked anything like a computer company in the last 15 years.”
This thoroughness sometimes backfired when pitching venture capitalists. Instantly jumping to an appendix slide for obscure startups—such as EJet or Elogex—served as a visceral reminder of dead investments, making some investors nervous that the team was overly fixated on industry failures. Alongside launching the company, Cantrill and co-founders Steve Tuck and Jess Frazelle recognized that practical wisdom at the hardware-software boundary was eroding, leading them to start *On the Metal*, a podcast exploring technical hardware and software lore across multiple engineering generations, including a recent interview with Star Simpson.
```mermaid flowchart LR accTitle: Oxide Computer Company Founding Milestones accDescr: Timeline of Oxide Computer Company from seed funding to production delivery.
A["Late 2019: Seed Round Closed"] --> B["Early 2020: 15-Person Team Ramped"] B --> C["2021 Target: Functional Prototype"] C --> D["2022 Target: Production Systems"] ```
[01:06:22](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3982s) Q&A: Ancestor Companies vs. Competitors
Opening the floor to questions, an audience member mentions historic hardware makers like Convex Computer and Multiflow from the mini-supercomputer era of the late 1980s and early 1990s. Cantrill recalls that Convex (later acquired by HP) reportedly had an outdoor cemetery on their Dallas campus where they physically engraved the tombstones of defeated competitors into concrete.
Cantrill observes that while keeping track of competition can be entertaining, studying dead predecessors is vastly more educational for an engineer:
> “It's more interesting, I think, to keep track of your ancestors than your competition, because I think they've got more to teach you than then you're—I mean it's easy to kind of disparage your competition, we never listen to that, but the it's the folks that seemed like they were the right place to the right time and and with the right technology and didn't succeed that aren't some ways more intriguing.”
[01:08:28](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4108s) The Target Market: The Pain of Cloud Costs and On-Prem Realities
When asked about Oxide's target demographic, Cantrill identifies organizations running compute on-premises. These customers fall into distinct buckets, frequently driven by strict regulatory constraints or staggering cloud expenditures that threaten company viability. For years, conventional industry dogma has insisted that running on-premises infrastructure is obsolete, treating those who remain as if they simply fail to comprehend modern cloud computing:
> “If you talk to these customers, they tend to be pretty animated because they're being told they don't exist, or to the degree they exist, it's like they exist because they're dummies who don't understand the cloud.”
Cantrill notes that cloud pricing structures are deceptively designed: they jump abruptly from practically zero—masked by investor subsidies or initial promotional credits—to staggering numbers that decimate a company's cost of goods sold (COGS). By the time leadership discovers they are being crippled by public cloud compute fees, migrating back on-premises proves excruciating. Off-the-shelf white-box and commercial servers are difficult to configure and operate without hyperscale-sized engineering teams, leaving frustrated operators with botched rack deployments and few viable alternatives.
- **Cloud Cost Trap**: Companies shift rapidly from "free" cloud credits to unsustainable monthly bills with very little warning or transitional pricing cushion. - **On-Prem Abandonment**: Enterprise IT vendors have treated on-premises customers as anachronisms, leaving them stranded with fragmented server hardware and poor software ergonomics.
[01:10:38](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4238s) The "Left for Dead" On-Prem Market and VC Reactions
While raising their financing round, Oxide arranged for prospective investors to conduct customer validation calls. Cantrill recalls being mindful of their design partners' time, only for customers to tell them enthusiastically: “Bring the VCs to me; I want to explain to them that I exist!” Venture capitalists frequently returned from these calls visibly shaken. When one investor reported back that the prospective customers seemed agitated, Cantrill explained that they were furious because the broader industry routinely tells them their market has vanished.
```mermaid flowchart LR accTitle: Evolution of the On-Premises Infrastructure Market accDescr: Diagram showing the two primary customer cohorts transitioning onto modern on-prem infrastructure. subgraph S1["Present Day"] A["Legacy Enterprises<br/>('Left for dead' on-prem)"] end subgraph S2["Next Decade"] B["Cloud-Native Companies<br/>(Approaching S-1 filing / IPO)"] end subgraph S3["Destination"] C["Rack-Scale On-Premises<br/>Hardware Infrastructure"] end A --> C B -->|"Scale & margin economics (COGS)"| C ```
Cantrill emphasizes that the on-premises market is indisputably real. Today, that market consists of teams that have been “left for dead on-prem,” but over the coming decades, it will increasingly be populated by companies that were originally born in the cloud and are forced back on-prem by basic unit economics. As Cantrill put it to the investors: “Yeah, no, they're angry—I hope you didn't tell them they don't exist, because they get very, very upset if you tell them that they don't exist.”
[01:12:04](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4324s) Choosing an ISA: Intel, AMD, ARM, and RISC-V
Asked about processor architectures, Cantrill clarifies his stance on the major vendors. He harbors no animus toward Intel, remarking only that he wished Intel had evolved into a full computer company long ago rather than strictly a microprocessor company afraid of competing with its own channel. As for Microsoft, Cantrill jokes that he has avoided their software ever since “Bill Gates robbed me of my childhood,” making them an irrelevance to Oxide's platform.
Turning to microprocessors, Cantrill evaluates the options for high-performance server workloads: - **RISC-V**: Excellent for embedded microcontrollers, soft cores on FPGAs, or bounded hard cores where hardware behavior must be verified and reasoned about, but “RISC-V is nowhere near ready to run modern heavy-duty workloads.” It cannot yet compete at the cutting-edge process nodes (like 7nm) required for maximum density and throughput. - **ARM**: AWS's Graviton2 (based on the Neoverse N1 / Ares core) is impressive, but for Oxide, ARM represents a lateral move away from x86 without a compelling performance or power advantage. - **x86 (AMD / Intel)**: Cantrill has no desire to reignite historical instruction set architecture battles, observing: “I fought the ISA war before, and I really don't want to fight it again; I have long since accepted that it's going to be x86 from an ISA perspective, at least for these kind of virtualized workloads.”
[01:14:00](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4440s) Cloud Economics and the S-1 Margin Threshold
Cantrill rejects the idea that Oxide is an “anti-cloud” company. On the contrary, he argues that elastic compute is transformative and that any new startup should unequivocally begin its life in the cloud. However, organizations reach an architectural turning point once they scale.
The economic calculus flips when a venture-backed growth software-as-a-service (SaaS) business prepares to file its S-1 registration statement to go public. At that juncture, financial scrutiny shifts to gross margins, and cloud hosting costs shift from an operating line item into cost of goods sold (COGS). When hosting bills begin to visibly erode corporate margins at high scale, moving foundational workloads back to physical, customer-owned machines becomes a financial necessity.
- Anyone starting a project should begin on public cloud infrastructure. - The shift back to physical hardware is triggered when cloud spend turns into an unacceptable COGS drag. - “And when you start to view the cloud as COGS, now it's probably time to start thinking about being on your own physical machine at the scale we're talking about.”
[01:15:20](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4520s) Low-Level Rust and Embedded Systems
Addressing whether Rust can access raw hardware as intimately as C, Cantrill answers that Rust is actually far more coherent for systems programming. In traditional C operating system codebases, blending assembly with C forces the developer into compiler “best-of-luck land,” where the compiler can make unpredictable assumptions across boundaries. Rust provides explicit, structured primitives to bypass calling conventions entirely when required, such as writing naked functions without standard ABI register-saving preambles: “You have got the ability to indicate that a function should have no preamble, should have basically like, 'I want to be out of ABI land in this function.'”
```mermaid flowchart TD accTitle: Rust vs C Low-Level Safety Primitives accDescr: Comparison of compiler constraints between C and Rust for systems and embedded development. subgraph C_Lang["Traditional C Approach"] C1["Mixed C and Inline Assembly"] C2["Compiler 'best-of-luck land'"] C3["Lint: false positive storms or silent overflow"] C1 --> C2 --> C3 end subgraph Rust_Lang["Rust Systems Approach"] R1["Explicit Primitives (e.g., naked functions)"] R2["Strict Type Boundaries (no implicit sign mixing)"] R3["Compile-time overflow checks & guaranteed ABI opt-outs"] R1 --> R2 --> R3 end ```
Cantrill predicts that just as RISC-V will capture computing from the bottom up in embedded microcontrollers, Rust will conquer embedded systems software first. Embedded firmware has historically been brutal to develop and verify using C. He points the audience to the blog series *Learning Rust the Dangerous Way* by Cliff Biffle (an engineer at Oxide) to illustrate the sophisticated techniques possible when writing bare-metal Rust directly on hardware.
[01:17:49](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4669s) Integer Overflows: Why Lint Fails and Rust Succeeds
The discussion turns to integer overflow vulnerabilities in systems languages. In C, developers must meticulously craft bounds checks to avoid accidental unsigned wraparound, and traditional linters provide virtually no defense. Linters cannot aggressively flag potential unsigned integer wrap conditions because doing so generates an overwhelming flood of false positives that leads engineers to silence or ignore the tooling altogether.
Cantrill notes that while critics might dismiss integer overflow bugs as merely bad coding, the sheer difficulty of avoiding them across millions of lines of code proves that existing C tooling is fundamentally inadequate. Rust resolves this structural problem at the language level by refusing to allow implicit, transparent mixing of signed and unsigned types, forcing explicit conversions and providing predictable overflow handling. “The reality is it's really, really hard for lint—lint would generate too many false positives was the reason that lint is not warning about that condition, and people would never use them because it would never shut up, whereas Rust is much more constrained about the way you're able to use it.”
[01:19:20](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4760s) High-Speed Board Design and Signal Propagation
Asked about the source of applications returning to on-premise hardware, Cantrill references companies like Uber, who have publicly detailed migrating substantial footprints out of the public cloud and back onto on-premises infrastructure to run their proprietary distributed services.
The conversation then pivots to the physical engineering hurdles of high-speed motherboard design. Cantrill caveats that board layout is not his personal domain of expertise, but highlights the intense physics involved in routing high-frequency memory lines. Because electrical signals propagate on printed circuit boards at roughly one picosecond per inch, the trace lengths between processor sockets and memory channels must be matched with extreme precision. At the gigahertz operating speeds of DDR3, DDR4, and emerging DDR5 standards, even microscopic discrepancies in trace length introduce significant timing skews that corrupt data transmission.
[01:20:48](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4848s) Memory Controller Physics and the Mechanics of DIMM Training
An audience member asks about DIMM training and memory tuning, prompting Bryan Cantrill to delve into the physical realities of modern high-speed memory interfaces. Cantrill explains that because signal traces across a motherboard introduce varying propagation delays and react to subtle environmental conditions like temperature and voltage fluctuations, the memory controller cannot simply speak to memory blindly. Instead, the controller must perform DIMM training—a calibration process where it figures out the exact electrical timing offsets and parameters needed to reliably bridge the CPU to memory across extremely high-frequency physical buses.
Cantrill points out that this training process takes measurable time, calculating complex constants that hardware vendors traditionally guard behind proprietary, opaque blobs. While memory controllers maintain awareness of the identity of the DIMM slotted into each channel, reseating or moving a DIMM forces a full retrain of the bus. Although Cantrill readily admits that low-level silicon memory physics sits slightly beyond his personal specialty, he emphasizes why system designers avoid retraining whenever possible: “this is it you're out of my domain of expertise but it is long enough that it's not something you want to do when you if you do if you can avoid it yes”. Historically, system boot and firmware engineers have lacked deep visibility into this training phase, turning it into a notoriously difficult, black-box step during server initialization.
- DIMM training calculates dynamic timing constants based on physical trace length, board impedance, and ambient environmental conditions. - Reseating a memory module or moving it between slots disrupts previously known parameters and forces the controller to execute a retraining cycle. - The process relies heavily on vendor-proprietary algorithms that have historically offered minimal transparency or debug visibility to systems software.
---
[01:23:07](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=4987s) Cloud De-coupling: Paring Down to Primitive Substrates
The conversation shifts to the broader software ecosystem when an audience question challenges whether a new on-premises hardware platform can succeed given that modern developers are hooked on high-level managed cloud services. Cantrill pushes back vigorously against the assumption that customers want total cloud vendor lock-in. While there was once an era when engineering organizations uncritically adopted every bespoke SaaS database or queuing system launched by public cloud providers, Cantrill argues that the pendulum has swung sharply in the opposite direction over the past half-decade.
Cantrill views the meteoric rise of Kubernetes and container platforms as an explicit revolt against vendor capture, allowing teams to reclaim autonomy over their operational runtime. Modern architects are deliberately avoiding sticky, proprietary offerings like Amazon Redshift, Amazon RDS, or SQS. Instead, they seek to strip their operational contract down to the absolute bare minimum: raw compute, block storage, and object storage. Cantrill states: “in my view people are really trying to pare down their dependencies to easy to EBS s3 and there are a logical go find another clouds with the idea being if you give me a say if you if you give me those services I can hydrate things up the stack but I don't want to actually build something out that's dependent upon RDS or depending upon you know sqs or what-have-you”. If a system can cleanly provide the equivalents of EC2, EBS, and S3, software developers can hydrate and run their own open-source stacks on top without becoming permanently shackled to a proprietary ecosystem.
```mermaid flowchart TD accTitle: Cloud Portability and Primitive Substrates accDescr: Diagram contrasting proprietary cloud services with a portable open substrate based on EC2, EBS, and S3 equivalents.
subgraph Proprietary["Proprietary Cloud Lock-In (Declining)"] A["Amazon Redshift / Specialized SaaS"] B["Amazon RDS / Proprietary Databases"] C["Amazon SQS / Managed Messaging"] end
subgraph Portable["Self-Hydrated Open Stack (Ascending)"] K8s["Kubernetes & Container Orchestration"] OpenApps["Open-Source Engines / Workloads"] end
subgraph Primitives["Core Commodity Primitives"] EC2["Compute (EC2 equivalent)"] EBS["Block Storage (EBS equivalent)"] S3["Object Storage (S3 equivalent)"] end
Primitives --> Portable Portable -.->|"Replaces"| Proprietary ```
---
[01:24:19](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=5059s) Toolchains, Modern Open Silicon, and Closing Remarks
Addressing an audience inquiry regarding development toolchains and cloud-hosted FPGAs, Cantrill acknowledges that services like Amazon Web Services' EC2 F1 instances allow developers to run hardware synthesis workloads remotely in the cloud. However, for Oxide's hands-on development style, they bypass hosted FPGA instances in favor of physical hardware development benches: “we don't use them because we're actually just doing an FPGA like the old-school way on what it would like a programmer and an FPGA it's sitting in front of you but those things do exist and they can be useful for certain applications it's my understanding”.
To conclude, Cantrill addresses whether Oxide's ambitious vision leaves them perilously dependent on external third parties delivering unproven technologies. He makes it clear that Oxide is riding a technological wave that is already mature and self-sustaining rather than speculative. Foundational elements like the Rust programming language have proven themselves to be battle-tested and production-ready for systems engineering. Hardware description ecosystems like Bluespec, Chisel, and SpinalHDL have already broken open, and RISC-V represents an open silicon reality that engineers can design and fabricate against immediately. Cantrill summarizes that while Oxide actively champions and contributes to these movements, the revolution is already unfolding across the industry on its own momentum: “we're not depending on anybody to deliver here in terms of these trends so the these are things that are already out there”. With that confident assessment of the hardware landscape, Cantrill thanks the Stanford audience, bringing the seminar to a close.
- Cloud-hosted FPGAs (like AWS EC2 F1 instances) serve specific remote validation needs, but direct local hardware programmers remain standard for rapid board bring-up. - Rust has matured beyond experimental status into a robust, production-grade language for writing systems and low-level firmware. - Open hardware and description languages—specifically RISC-V, Bluespec, Chisel, and SpinalHDL—provide an open ecosystem that permits new hardware companies to innovate without waiting on legacy proprietary toolchains.
## Notable quotes > [55:28](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3328s) With C you could feel the underlying assembly; with Rust you can feel the underlying C. — Bryan Cantrill
> [26:19](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1579s) Your job is to bring the host operating system its cup of coffee and shoot yourself in the head; that should be the role of host firmware. — Bryan Cantrill
> [40:42](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=2442s) It was easier to get a hardware company funded two decades ago, but hardware has never been easier than it is today. — Bryan Cantrill
> [29:22](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1762s) Interoperability is great in principle, but it is very corrosive when you want to make an actual tight integrated design. — Bryan Cantrill
> [52:47](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3167s) I fervently believe that Rust is every bit as important revolution as C. — Bryan Cantrill
> [29:22](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=1762s) By rack-scale design, I mean really thinking about the entire rack; taking a bunch of 2Us and slapping it into a rack is not a rack-scale design, that is just rack and stack. — Bryan Cantrill
> [50:32](https://www.youtube.com/watch?v=vvZA9n3e5pc&t=3032s) I don't want garbage collection anywhere near the systems that I'm developing. — Bryan Cantrill
## Mentioned Bryan Cantrill, Jon Masters, Tracy Kidder, David Patterson, Steve Klabnik, Steve Tuck, Jess Frazelle, Star Simpson, Amit Levy, Phil Levis, Bill Gates, Cliff Biffle, Rick Altherr, The Soul of a New Machine, Data General Eclipse MV/8000, IBM 709, Compatible Time-Sharing System (CTSS), Hughes Aircraft, Digital Equipment Corporation (DEC), PDP-11/70, Raspberry Pi, Sun Microsystems, Sun Enterprise 10000, UltraSPARC, eBay, Intel, SPARC, IBM POWER, PA-RISC, DEC Alpha, HP ProLiant DL380 Gen5, IBM PC, Intel 8259 PIC, Google, Gigabyte, Facebook, Open Compute Project (OCP), Tioga Pass, Wedge, Bryce Canyon, Oracle, Joyent, Samsung, Amazon Web Services (AWS), American Megatrends Inc. (AMI), Bloomberg, Supermicro, Aspeed, Nuvoton, Intel Management Engine (ME), AMD Platform Security Processor (PSP), MINIX, General Electric, Barclays, General Motors, Project Cerberus, Google Titan, OpenTitan, Chromebook, Bluespec, Yosys, Chisel, SpinalHDL, RISC-V, Open Source Firmware Conference (OSFC), Coreboot, LinuxBoot, Apache ZooKeeper, DTrace, Tock OS, On the Metal, Convex Computer, Multiflow, AMD, ARM, AWS Graviton2, Neoverse N1, Uber, Kubernetes, Amazon EC2, Amazon EBS, Amazon S3, Amazon Redshift, Amazon RDS, Amazon SQS, EC2 F1, Rust, Oxide Computer Company
## Video description Bryan Cantrill Oxide Computer Company
February 26, 2020 While our software systems have become increasingly elastic, the physical substrate available to run that software (that is, the computer!) has remained stuck in a bygone era of PC architecture. Hyperscale infrastructure providers have long since figured this out, building machines that are fit to purpose -- but those advances have been denied to the mass market. In this talk, we will talk about our vision for a new, rack-scale, server-side machine -- and how we anticipate advances like open firmware, RISC-V, and Rust will play a central role in realizing that vision.
View the full playlist: https://www.youtube.com/playlist?list=PLoROMvodv4rMWw6rRoeSpkiseTHzWj6vu
► Check out our entire catalog of courses and programs: https://online.stanford.edu/explore
[Source](https://www.youtube.com/watch?v=vvZA9n3e5pc)