Sam Zeloof Produces 1,200-Transistor Silicon Chip in Garage Fab

"Z2" - Upgraded Homemade Silicon Chips — Sam Zeloof

Sam Zeloof

A self-aligned polysilicon gate process drops threshold voltage to one volt, enabling homemade integrated circuits to run on standard digital logic rails.

AI-assisted summary of "Z2" - Upgraded Homemade Silicon Chips — original source. Check the original for full context.

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Key ideas

  • Sam Zeloof introduced the Z2 integrated circuit, featuring 100 transistors per die across a 12-die array for a total of 1,200 transistors on a single homemade silicon chip. (0:00)
  • A shift to a self-aligned polysilicon gate process reduced the threshold voltage to approximately 1V, enabling standard 3.3V and 5V logic compatibility without high-voltage 9V batteries. (0:00)
  • Photolithography was executed using a DIY maskless stepper based on a DLP projector and a standard laptop display, eliminating expensive physical chrome reticles. (1:21)
  • High-temperature drive-in diffusion at over 1000°C for 45 minutes using spin-on liquid phosphorus created the n-type source and drain wells. (3:12)
  • Analytical probe station measurements confirmed textbook-grade n-channel MOSFET ID-VDS saturation and linear curves on the finished silicon. (4:40)

Detailed notes

## Background Published on YouTube by independent hardware hacker Sam Zeloof on August 13, 2021, this video showcases his upgraded homemade silicon integrated circuit fabrication process, humorously summarized as 'dipping a rock into chemicals until it becomes a computer chip.' The project log highlights his second-generation chip architecture while referencing pioneering homebrew semiconductor work by Jeri Ellsworth.

## TL;DR Sam Zeloof introduces the Z2, an upgraded homemade integrated circuit featuring a 12-die array totaling 1,200 transistors built with a self-aligned polysilicon gate process. Transitioning from high-voltage prototypes to ~1V threshold logic compatible with standard 3.3V and 5V systems, the fabrication flow relies on scribed wafer squares patterned using an innovative DIY maskless DLP projection stepper. After drive-in phosphorus diffusion in a tube furnace at over 1000°C, dielectric contact etching, and thermal evaporation of aluminum interconnects, the chip is completed and inspected under a microscope. Analytical probe testing with sub-millimeter tungsten needles verifies textbook MOSFET current-voltage curves, validating successful transistor operation from a garage cleanroom.

## Atmosphere & style The presentation is remarkably calm, methodical, and understated, presenting jaw-dropping garage engineering with the casual familiarity of a weekend workshop craft. Zeloof's soft-spoken, matter-of-fact narration demystifies advanced solid-state physics, transforming hazardous chemicals and quartz tube furnaces into approachable benchtop steps. Watching the sequence feels hypnotic and deeply satisfying, evoking quiet awe as raw silicon squares gradually reveal intricate microscopic circuitry that performs to textbook standards.

## Bulletin - [00:00](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=0s) Sam Zeloof introduced the Z2 integrated circuit, featuring 100 transistors per die across a 12-die array for a total of 1,200 transistors on a single homemade silicon chip. - [00:00](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=0s) A shift to a self-aligned polysilicon gate process reduced the threshold voltage to approximately 1V, enabling standard 3.3V and 5V logic compatibility without high-voltage 9V batteries. - [01:21](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=81s) Photolithography was executed using a DIY maskless stepper based on a DLP projector and a standard laptop display, eliminating expensive physical chrome reticles. - [03:12](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=192s) High-temperature drive-in diffusion at over 1000°C for 45 minutes using spin-on liquid phosphorus created the n-type source and drain wells. - [04:40](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=280s) Analytical probe station measurements confirmed textbook-grade n-channel MOSFET ID-VDS saturation and linear curves on the finished silicon.

## Key takeaways - [00:00](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=0s) The Z2 chip scales homebrew semiconductor density to 1,200 total transistors across 12 dies, approaching early commercial milestones like Intel's first processor. - [00:24](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=24s) Adopting a self-aligned polysilicon gate drops threshold voltages to ~1V, allowing direct compatibility with 3.3V and 5V logic rails. - [00:47](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=47s) The 4-layer mask set for the chip was designed directly in Adobe Photoshop rather than specialized EDA software. - [01:04](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=64s) Production-grade 200 mm silicon wafers are cleaved into half-inch working squares using a diamond scribe to fit benchtop processing tools. - [01:21](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=81s) Spin coating applies positive photoresist at 4,000 RPM for 30 seconds before a 95°C soft bake. - [01:45](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=105s) A DIY maskless stepper projects blue light patterns via a DLP projector, exposing each die field in about nine seconds. - [02:08](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=128s) Wafers are developed in a dilute ~2% KOH solution and can be stripped with acetone and reworked if defects appear. - [03:12](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=192s) Liquid spin-on dopant containing phosphorus is diffused in a quartz tube furnace at >1000°C for 45 minutes to form n-type regions. - [03:55](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=235s) Thick thermal silicon dioxide dielectric layers are etched using hydrofluoric acid or CHF3 reactive ion etching (RIE) to open contact vias. - [04:14](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=254s) Approximately 1 µm of aluminum interconnect is deposited via thermal evaporation and patterned with warm phosphoric acid wet etching. - [04:40](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=280s) Finished dies undergo optical inspection under a microscope to measure critical dimensions such as gate length, gate width, and film thickness. - [04:53](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=293s) Micro-manipulated tungsten probe needles on an analytical station land manually on integrated pads to capture electrical characteristics. - [05:14](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=314s) Automated parametric sweeps demonstrate clean ID vs. VDS curve families with distinct linear and saturation regimes matching reference textbook MOSFET behavior.

## Detailed walkthrough ### [00:00](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=0s) The Z2 Chip: Architecture and Upgraded Polysilicon Process

A few years after building the world's first homemade silicon chip in his garage fab, Sam Zeloof introduced the Z2, an upgraded integrated circuit featuring 100 transistors per individual die. Fabricated as an array of 12 dies across a single piece of silicon, the total transistor count reaches 1,200 devices. Reflecting on this density milestone relative to computing history, Sam Zeloof observed: “Intel's first processor had only 2,000 transistors so we're already approaching a decent level of complexity and I should be able to make some really interesting circuits out of this soon.” While earlier test projects with the first-generation chip—such as an LED flasher and a guitar distortion pedal—functioned properly, their high threshold voltages demanded one or two 9-volt batteries to operate.

The Z2 transitions to a self-aligned polysilicon gate process, fundamentally altering electrical performance. This change drops the threshold voltage down to approximately 1 volt, enabling direct compatibility with standard 3.3-volt and 5-volt logic systems, reducing total power draw, and allowing significantly tighter transistor packing inside a smaller die area. Rather than turning to heavyweight electronic design automation (EDA) software, the mask design for this four-layer process was drafted entirely in Adobe Photoshop, which proved far simpler for chips of this scale. The physical fabrication begins with 200 mm production-grade silicon wafers chosen for specific starting specifications. Because full-sized wafers are too large for the benchtop setup, they are diced with a diamond scribe into half-inch square samples, though the tooling can accommodate substrates up to two inches across.

- **Transistor count**: 100 transistors per die; 12-die array yields 1,200 transistors on a single chip. - **Operating voltage**: Drop from high-voltage 9V battery operation to ~1V threshold voltage, running on 3.3V and 5V logic rails. - **Substrate handling**: 200 mm silicon wafers cleaved down to ~0.5-inch working squares using a diamond scribe. - **Mask design**: 4 lithography layers drafted directly in Adobe Photoshop.

[01:21](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=81s) Lithography and Patterning with a DIY Maskless Stepper

Patterning the first layer—the doped source and drain regions—begins on a custom-built spin coater. A tiny drop of positive photoresist, roughly 100 microliters, is dispensed onto the wafer piece and spun at 4,000 RPM for 30 seconds to produce a uniform coating. The wafer is then transferred to a hot plate for a soft bake at 95°C for one minute, driving off residual solvent carriers to leave behind an even, solid film across the silicon surface.

```mermaid flowchart TD accTitle: Z2 Photolithography Cycle accDescr: Step-by-step lithography process from resist coating through exposure, development, and etching. subgraph Coating["Resist Application"] A["Spin Coat Resist<br/>100 µL @ 4000 RPM"] --> B["Hot Plate Soft Bake<br/>95°C for 1 min"] end subgraph Exposure["Pattern Exposure"] B --> C["Maskless Stepper<br/>DLP Projection (9s)"] end subgraph Processing["Wet Processing"] C --> D["Develop in KOH<br/>~2% solution, 1 min"] D --> E["Water Rinse & Inspect<br/>Rework with acetone if needed"] E --> F["Chemical Etch<br/>Transfer pattern to film"] F --> G["Resist Strip<br/>Acetone bath"] end ```

The sensitized wafer moves to a homemade maskless photolithography stepper. Instead of expensive physical chrome-on-glass reticles, a laptop loads the mask image and feeds it to an onboard DLP projector. Projection optics reduce the image down to a miniature blue exposure field focused onto the die area. Each exposure takes about nine seconds, after which the blue light turns off and the stage steps to adjacent positions to expose the rest of the array. The exposed wafer is immersed in a dilute potassium hydroxide (KOH) developer solution (around 2%) for one minute, which washes away the exposed positive resist before being rinsed in water. Sam notes the forgiving nature of the step: if an inspection under the optical microscope reveals defects, the photoresist can simply be stripped off with acetone and recoated under adjusted exposure or development times. Once verified, the pattern is chemically etched into the underlying polysilicon layer, and the remaining resist mask is stripped away with acetone.

- **Spin coating parameters**: 100 µL positive photoresist, 4,000 RPM, 30-second cycle. - **Pre-bake**: 95°C hot plate for 60 seconds. - **Lithography system**: Maskless DLP optical reduction stepper running off a standard laptop display. - **Exposure cycle**: 9-second blue light projection per die field. - **Development**: ~2% KOH aqueous developer for ~60 seconds, followed by a DI water rinse. - **Stripping agent**: Acetone to dissolve photoresist masks after wet etching.

[03:12](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=192s) High-Temperature Doping, Dielectric Etch, and Metallization

With the source and drain regions opened, the wafer is cleaned, dried, and prepared for thermal diffusion. Sam deposits a liquid spin-on dopant—phosphorus dissolved in a liquid silicon dioxide matrix—using the spin coater in the same manner as the photoresist. The wafer is loaded into a quartz diffusion tube furnace using a quartz push rod, positioning it in the hot zone at over 1000°C for approximately 45 minutes. This thermal drive-in forces phosphorus atoms deep into the exposed silicon wells, creating n-type conductive source and drain regions before the boat is pulled from the furnace tube.

```mermaid flowchart LR accTitle: Z2 High-Temperature Doping and Metallization Flow accDescr: Sequence showing dopant diffusion, gate and contact lithography, dielectric etching, and aluminum metallization. subgraph Diffusion["Doping Phase"] A["Spin-on Phosphorus"] --> B["Furnace Drive-In<br/>>1000°C, 45 min"] end subgraph GateContact["Gate & Contact Layering"] B --> C["Gate Litho & Etch<br/>Polysilicon Etchant"] C --> D["Contact Mask Litho"] D --> E["SiO2 Dielectric Etch<br/>HF or CHF3 RIE"] end subgraph Metal["Interconnect"] E --> F["Thermal Evaporation<br/>~1 µm Aluminum"] F --> G["Metal Lithography"] G --> H["Phosphoric Acid Etch<br/>Warm bath"] end ```

The complete photolithographic sequence—spin coating, soft baking, stepper exposure, and development—is repeated twice more to form the gate and contact levels. The gate layer is etched using polysilicon wet etchant. Because the 1000°C diffusion stage leaves a thick, insulating layer of silicon dioxide across the entire surface, the contact vias require an aggressive dielectric removal process using either hydrofluoric acid (HF) wet etching or carbon trifluoride (CHF3) reactive ion etching (RIE) to uncover bare silicon for low-resistance connections. The wafer is then placed inside a high-vacuum chamber where a thick layer of aluminum (approximately one micron) is deposited, primarily via thermal evaporation. A final round of photolithography patterns the metal interconnect traces, followed by immersion in a warm phosphoric acid bath to strip residual aluminum and isolate the circuits.

- **Dopant chemistry**: Phosphorus suspended in liquid silicon dioxide (spin-on dopant). - **Drive-in diffusion**: >1000°C tube furnace for 45 minutes using quartz tooling. - **Dielectric oxide stripping**: Hydrofluoric acid (HF) dip or CHF3 reactive ion etching (RIE). - **Metallization thickness**: ~1 µm thermally evaporated aluminum layer. - **Metal etching**: Warm phosphoric acid bath.

[04:40](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=280s) Wafer Inspection, Probe Testing, and Transistor Characterization

Once metal etching is complete, the finished wafer undergoes detailed optical inspection under a microscope. Sam captures high-magnification photomicrographs to verify alignment and measure critical dimensions, including gate length, gate width, and film thicknesses, occasionally checking cross-sections. Electrical testing takes place on an analytical probe station equipped with micro-positioners holding extremely fine tungsten needles, which must be manually landed on tiny contact pads. Highlighting the physical difficulty of this stage, Sam remarks: “It's very finicky and these transistors are so small that it's not actually that trivial to make contact to them but anyway I boot up all this test equipment that allows me to characterize them.”

Automated parametric test instruments, controlled via custom test software, sweep voltages across the terminal pins to evaluate device physics. The key readout is the drain current versus drain-to-source voltage ($I_D$ vs. $V_{DS}$) curve family across varying gate biases for the homemade n-channel MOSFETs. When plotted, the output curves display clean saturation plateaus and sharp linear regimes that closely match ideal textbook curves sourced from reference literature. Satisfied with the yield and gate control of the Z2 architecture, Sam concludes by addressing viewer interest in funding garage fabrication hardware, noting that a Patreon link has been established to support future homebrew semiconductor experiments.

- **Inspection targets**: Gate width, gate length, layer alignment, cross-sectional thickness. - **Probe setup**: Micro-manipulated tungsten needles contacting miniature integrated pads. - **Electrical validation**: $I_D$ versus $V_{DS}$ curve family confirms proper n-channel MOSFET operation and active pinch-off/saturation behavior.

## Notable quotes > [00:00](https://www.youtube.com/watch?v=IS5ycm7VfXg&t=0s) Intel's first processor had only 2,000 transistors so we're already approaching a decent level of complexity and I should be able to make some really interesting circuits out of this soon. — Sam Zeloof

## Mentioned Sam Zeloof, Z2, Intel, Adobe Photoshop, Jeri Ellsworth, Patreon, YouTube

## Video description https://www.patreon.com/szeloof

http://sam.zeloof.xyz/second-ic/

Check our Jeri Ellsworth's amazing work making the first transistors and logic gates at home https://www.youtube.com/watch?v=PdcKwOo7dmM&t=1s

Dipping a rock into chemicals until it becomes a computer chip Upgraded Homemade Silicon IC Fab Process

[Source](https://www.youtube.com/watch?v=IS5ycm7VfXg)

中文简报

Sam Zeloof在车库晶圆工坊制造出含1200个晶体管的硅芯片 自对准多晶硅栅工艺将阈值电压降至1伏，使自制集成电路能够在标准数字逻辑供电轨下运行。 Sam Zeloof推出了升级版自制集成电路Z2，该芯片采用自对准多晶硅栅工艺构建，包含由12个管芯组成、总计1200个晶体管的阵列。与早期的高压原型不同，该工艺过渡到了与标准3.3V和5V系统兼容的约1V阈值电压逻辑；其制造流程基于划片后的方形晶圆片，并采用创新的自制无掩模DLP投影光刻机进行图案化。在管式炉中经受超过1000°C的磷推进扩散、介质接触孔刻蚀以及铝互连线热蒸发后，芯片制作完成并在显微镜下接受检查。使用亚毫米钨探针进行的分析性探针测试证实了教科书级别的MOSFET电流-电压曲线，验证了车库超净间成功制造出可正常工作的晶体管。 Sam Zeloof推出了Z2集成电路，每个管芯包含100个晶体管，在由12个管芯组成的阵列中共计拥有1200个晶体管，集成在单块自制硅芯片上。 (0:00) 转向自对准多晶硅栅工艺将阈值电压降低至约1V，无需使用9V高压电池即可兼容标准的3.3V和5V逻辑电平。 (0:00) 光刻工序采用了基于DLP投影仪和标准笔记本电脑显示屏的自制无掩模步进式光刻机完成，省去了昂贵的实体铬版光掩模。 (1:21) 利用旋涂液态磷源在超过1000°C的高温下进行45分钟推进扩散，形成了n型源极和漏极阱区。 (3:12) 分析探针台测量证实了成品硅片上呈现出教科书级别的n沟道MOSFET ID-VDS饱和与线性特性曲线。 (4:40)

Source quotes

[0:00] Sam Zeloof: Intel's first processor had only 2,000 transistors so we're already approaching a decent level of complexity and I should be able to make some really interesting circuits out of this soon.

Original transcript

[0:00] a few years ago i made the world's first [0:01] homemade silicon chip in my garage fab i [0:04] just made version 2 which has 100 [0:06] transistors on it and they're smaller [0:08] better and faster than the old one [0:10] i made an array of 12 of these so that's [0:12] 1 200 transistors on the same piece of [0:15] silicon intel's first processor had only [0:17] 2 000 transistors so we're already [0:19] approaching a decent level of complexity [0:21] and i should be able to make some really [0:22] interesting circuits out of this soon i [0:24] did some cool projects with my first [0:25] chip like a led flasher and a guitar [0:28] distortion pedal they worked really well [0:30] but needed one or two nine volt [0:31] batteries attached to them because the [0:33] threshold voltage of the old mosfets [0:35] were really high [0:36] this new chip is made on a polysilicon [0:38] gate process all these details are on [0:40] the write up on my blog but the effect [0:42] of that is that they work well at very [0:44] low voltages they have a threshold [0:45] voltage of only about 1 volt and that [0:48] means that i can power them off of 3.3 [0:51] and 5 volt logic levels they draw less [0:53] power and i should be able to pack more [0:55] of them into a smaller die area for [0:58] simple chips like this the process [0:59] actually starts in photoshop there's [1:01] only four layers to design and it's [1:03] easier to use this than to use some more [1:05] complicated software [1:07] i start with a lot of 200 millimeter [1:08] wafers that have some pretty specific [1:10] starting parameters they're way too big [1:12] so i dice them up using a diamond scribe [1:14] into smaller bits i normally do about [1:16] half inch squares like this but i can [1:17] process larger things up to about two [1:19] inch wafers [1:21] the first layer to define is the doped [1:23] layer that makes the source and drains [1:25] the mosfets i put it on this homemade [1:27] spin coater and then i deposit [1:29] photoresist on top of it you only need [1:31] about 100 microliters or so to cover a [1:33] small wafer like this and we spin it at [1:35] 4000 rpm for 30 seconds [1:39] after all the excess photoresist has [1:40] been spun off it's dried on a hot plate [1:42] at about 95 degrees c for one minute [1:44] this drives off the rest of the solvents [1:46] and leaves us with a solid film [1:49] the result is a beautiful looking and [1:51] uniform covering of the whole wafer [1:55] then it's off to the homebuilt maskless [1:57] photolithography stepper for exposure [1:59] the basic idea is that we load up an [2:01] image on this laptop that we want to [2:03] project onto the chip then there's a [2:05] standard dlp projector and some optics [2:07] that shoot that down and reduce it onto [2:09] the wafer i have a whole video on this [2:10] tool so i recommend checking that out in [2:13] the center you see a little blue dot [2:14] that's the entire exposure field it [2:16] lasts about nine seconds then the blue [2:19] goes away at the end of the exposure we [2:20] can step the wafer to another location [2:22] and expose that part too [2:25] just like processing filament a dark [2:27] room the next step is development i put [2:29] it in a couple percent potassium [2:30] hydroxide solution for about a minute [2:32] and this etches away the parts of the [2:34] photoresist that were exposed because [2:35] it's a positive photoresist [2:40] i wash it with water to get rid of the [2:42] residual developer and then we're ready [2:44] to do the next step i can put under a [2:46] microscope to inspect it and make sure [2:47] everything worked out well if it didn't [2:49] you can always just strip off the [2:50] photoresist layer and try again with [2:52] maybe a different exposure or [2:53] development time [2:56] now the image is formed in the [2:57] photoresist i transfer that into the [2:59] underlying polysilicon layer using an [3:01] etchant once it's etched we don't need [3:03] the photoresist mask layer anymore so [3:05] that can be stripped off using acetone [3:12] the wafer is then cleaned and dried and [3:14] we spin on a dopant this is a [3:16] phosphorous solution that's suspended in [3:19] a liquid silicon dioxide this is spun on [3:22] just like the photoresist and then we [3:23] bake it at very high temperature over [3:25] 1000 degrees c for about 45 minutes this [3:28] drives in the phosphorus atoms into the [3:31] little wells that we just defined using [3:32] lithography and that basically forms the [3:35] source and drains of the mosfets i have [3:37] to push it into the center of the [3:38] furnace using this quartz rod and then [3:41] at the end of the process we pulled out [3:42] the other side the process of spin [3:44] coating photoresist baking it exposing [3:46] it and developing it is then repeated [3:48] exactly twice once for the gate layer [3:50] and then again for the contact the gate [3:52] is etched just like we did before with [3:54] the polysilicon etchant and the contact [3:57] layer has to be etched as well because [3:59] now after the high temperature step [4:01] there's a layer of silicon dioxide [4:02] insulating everything so after the [4:04] contact mask is formed you have to use [4:06] something like hydrofluoric acid or [4:09] chf3 [4:10] reactive ion etching to get rid of that [4:12] insulator so we can make good electrical [4:14] contact [4:15] then we stick the wafer into a vacuum [4:17] chamber to either sputter or thermally [4:19] evaporate metal i'm evaporating aluminum [4:21] a thick layer of about a micron or so [4:24] and then we do the whole [4:25] photolithography process again of spin [4:27] coating and exposing and developing to [4:30] define that metal layer [4:32] once that's done stick the wafer into a [4:34] warm phosphoric acid bath that etches [4:36] off the residual aluminum and finally [4:39] the chip is done [4:40] at this point i'll inspect the chip [4:42] pretty thoroughly and take a lot of [4:43] close-up pictures to measure parameters [4:45] like gate length and width and layer [4:47] thicknesses if i do a cross-section i [4:49] can put it on the probe station which [4:50] has a bunch of really small tungsten [4:52] needles and allow me to make connections [4:54] directly to the transistors it's very [4:56] finicky and these transistors are so [4:58] small that it's not actually that [5:01] trivial to make contact to them but [5:03] anyway i boot up all this test equipment [5:06] that allows me to characterize them i do [5:08] a little bit of programming to define [5:10] the kind of tests i want to do and then [5:12] hopefully we're greeted with this great [5:15] curve so this is the [5:17] id versus vds curve of an n channel [5:20] mosfet here's an ideal one [5:22] taken off of the internet and then [5:24] here's the one that i'm getting from my [5:26] fets and they look great [5:28] i hope you found that interesting and [5:29] enjoyed learning about my second [5:31] integrated circuit i got a bunch of [5:32] requests to set up a patreon or [5:34] something like that i'm not sure if [5:35] that's the best way to do it but i'll [5:37] put a link in the description if you [5:39] want to support more homebrew [5:40] semiconductor fabrication experiments [5:42] like this [5:43] thanks for watching