Jane Street Announces Protocol Emulator ASIC Competition with Fabrication Funding

Jane Street Announces Protocol Emulator ASIC Competition with Fabrication Funding Jane Street has announced an open-source hardware competition challenging participants to design a general-purpose protocol emulator ASIC. Selected winning designs will be funded for fabrication via a Tiny Tapeout shuttle on IHP's 130nm process. Participants must design an open-source protocol emulator capable of implementing protocols like UART, SPI, and I2C via reprogrammable firmware rather than fixed logic. Targeting IHP's 130nm CMOS5L process via Tiny Tapeout, designs are capped at a 6x4 tile area (approx. 0.7 mm²), with a potential increase to 8x4. Winners will receive fabricated chips mounted on development boards targeting the March 2027 CMOS5L shuttle. Submissions are due by January 18, 2027, and team participation is strongly recommended. Design Challenge and Capabilities The competition requires designing a tiny CPU with an instruction set focused on reading/writing pins and precise cycle counting to emulate hardware protocols in software. Rather than incorporating fixed logic blocks for standard interfaces, the ASIC must remain reprogrammable after fabrication to accommodate new protocols under timing and I/O limits. Base targets are UART, SPI, and I2C, with stretch goals including low-speed USB and 10Mbit Ethernet, as well as interfaces such as JTAG, SWD, PS/2, and CAN bus. Process Parameters and Resource Budget The competition targets IHP's 130nm CMOS5L process using Tiny Tapeout tooling. The current design footprint is restricted to a 6x4 tile layout (24 tiles total, roughly 0.7 mm²), offering an estimated budget of about 1,000 logic cells per tile, though Jane Street is exploring scaling to 8x4 tiles. Participants are advised to leverage SRAM for instruction memory to conserve space, run synthesis and place-and-route early, and manage routing and clock-tree constraints. Rules, Timeline, and Rewards Submissions must be open source and submitted by January 18, 2027. Jane Street welcomes novel design and verification approaches, including formal methods, constrained random testing, and AI-assisted verification. Winning designs will be funded for fabrication on a Tiny Tapeout shuttle targeted for March 2027, with winners receiving mounted chips on development boards for silicon testing.

Jane Street 举办协议仿真器 ASIC 设计竞赛，出资为优胜方案流片 Jane Street 宣布举办开源通用协议仿真器 ASIC 设计竞赛，鼓励参赛者设计可通过固件重新编程来模拟多种硬件协议的专用芯片，优胜者将获得官方赞助的芯片流片及开发板。 竞赛任务是设计一款开源、通用的协议仿真器 ASIC，需支持 UART、SPI、I2C 等协议，并可拓展至低速 USB、10Mbit 以太网等。 芯片工艺采用 IHP 130nm CMOS5L，基于 Tiny Tapeout 平台，设计尺寸暂定为 6x4 瓦片（约 0.7 平方毫米、约 24K 逻辑单元）。 设计需完全开源，建议组队参加，最终提交截止时间为 2027 年 1 月 18 日，计划搭乘 2027 年 3 月的 CMOS5L 班车流片。 挑战目标与设计重点 参赛者需要设计一个微型 CPU 架构的协议仿真器，通过精细控制引脚读写与时钟周期来实现“bit-bang”协议通信，而非简单拼凑固定的硬件模块。芯片必须具备足够的灵活性，以便在制造后仍能通过固件重新编程支持新协议，基础目标包括 UART、SPI 和 I2C，扩展目标包含低速 USB、以太网、JTAG、SWD、PS/2 和 CAN 总线等。主办方也鼓励采用形式化验证、随机约束测试或 AI 辅助验证等新方法。 制造工艺与面积约束 设计将基于 Tiny Tapeout 合作的 IHP 130nm CMOS5L 工艺。当前上限面积为 6x4 瓦片（24 个瓦片，单瓦片约 200um × 150um，总标称面积约 0.7 mm²），主办方正评估扩展至 8x4 瓦片的可能。每个瓦片大约可容纳 1000 个逻辑单元，建议使用 SRAM 代替触发器以节省指令内存空间，并尽早进行综合、布局布线与时序检查以防布线拥塞或降频。 参赛规则与时间规划 提交的作品必须开源，参赛者可在公开环境中开发并强烈建议组队参赛。设计提交截止日期为 2027 年 1 月 18 日。Jane Street 将资助最具创新性的设计搭乘预定于 2027 年 3 月的 Tiny Tapeout 班车流片，优胜团队将收到封装好的实物芯片和开发板以在真实硅片上测试功能。

Last month, we asked you to reverse engineer a chip from nothing but its layout and teased a bigger challenge. Results and our favorite writeups are coming soon. In the meantime, here’s our next challenge! This time, you’re designing the chip, and we’ll pay to fabricate our favorite designs! We’re particularly interested in projects with unique functionality, as well as those that demonstrate novel approaches to design and verification methodologies! Winners will receive a fabricated copy of their chip, mounted on a dev boards, so they can test their design in real silicon. The challenge Design an open-source, general-purpose protocol emulator ASIC . Hardware protocols like UART, SPI, and I2C are simple enough that people routinely “bit-bang” them: toggle pins from software with careful timing instead of using a dedicated peripheral. A protocol emulator is a small chip built to do exactly that: a tiny CPU with an instruction set designed for reading pins, writing pins, counting cycles, and hitting timing precisely enough that you can implement a real protocol in firmware rather than in fixed logic. Something like that is a useful tool for hardware debugging and reverse engineering, which is a good part of what we do. The hard part is flexibility. The goal isn’t to put a UART block, an SPI block, and an I2C block on one die and call it done. Your chip should be reprogrammable enough to support new protocols after fabrication, within its timing and I/O constraints. For inspiration, look at the PIO state machines on the RP2040 or the PRU cores on TI’s Sitara parts, and consider what you’d do differently. Start with UART, SPI, and I2C. Stretch goals include low-speed USB and 10Mbit Ethernet. Other interesting protocols to consider: JTAG, SWD, PS/2, CAN bus If you have access to an FPGA, consider using it to test your RTL before the ASIC flow. Show us anything else your architecture makes possible that we haven’t thought of. At Jane Street, we use Hardcaml to generate the RTL for our FPGA and ASIC designs. We are excited to see the languages and verification techniques you use, including formal methods, random constrained tests, AI-assisted verification, and more. As AI-assisted chip design becomes more common, we believe verification will be an extremely important aspect of the ASIC design flow going forwards. The rules Process: We’re targeting IHP’s 130nm CMOS5L process through our friends at Tiny Tapeout . Start with the CMOS5L Verilog template , which takes you from RTL to GDS. Set the tile size in info.yaml to 6x4. Area: The current maximum area is 6x4 tiles per design. We are working on the possibility of scaling up to 8x4 tiles (~30% more area). We’ll update this page, as well as emailing everyone who has signed up if the larger tile size becomes available. Open source: Your submission should be open source so others can use and build on it. Unlike the reverse-engineering puzzle, there’s no need to keep your work hidden until the deadline, so feel free to build in public! Teams: This is a much bigger project than the puzzle, so we strongly recommend working in teams. Deadline: Submit your design by January 18th, 2027 . Prize: We’ll pay to tape out the most novel designs on a Tiny Tapeout shuttle. We’re targeting the March 2027 CMOS5L shuttle , subject to the foundry schedule. Winners will receive chips and dev boards back after fabrication, so you can test your design in silicon. How much fits? An 6x4 allocation is 24 tiles. At approximately 200um × 150um per tile, that’s about 0.7 mm² of nominal tile area. As a rough estimate, budget for about 1K logic cells per tile. You may need to get creative to fit the functionality you want. For instruction memory, SRAM can be more area-efficient than flip-flops. Tiny Tapeout has examples of SRAM running on this process node you can reference. Run synthesis early, check the mapped cell area, and leave room for clock-tree buffers and routing. Then run the full place-and-route flow and check timing. A design that looks small enough after synthesis can still be difficult to route or too slow at your chosen clock frequency. Getting started If you’ve never taped out a chip before, the Tiny Tapeout documentation walks through the process end to end, and the tools are all free and open source. Start by getting a UART transmitter out of a pin. Then make it programmable. Sign-up If you’re interested, please fill out our sign-up form . We’ll send updates about the tapeout template, deadlines, as well as providing the final submission link. Note that filling out the form is not a commitment to participating, it’s just to receive updates! We’ll add a final submission form to this page closer to the deadline! If you have questions along the way, reach out to asic-competition@janestreet.com . Hardware at Jane Street The hardware team at Jane Street designs FPGAs and ASICs that run some of the fastest trading systems in the world. If designing a chip for fun sounds like your kind of thing, take a look at our hardware internships and full-time roles . You can also explore Hardcaml , our open-source OCaml hardware design libraries, or stay in touch .