Jane Street Releases ASIC Reverse-Engineering Puzzle Ahead of Chip Design Contest

Jane Street Releases ASIC Reverse-Engineering Puzzle Ahead of Chip Design Contest Jane Street has published a hardware puzzle challenging participants to reverse engineer an ASIC given only its physical layout mask and sample inputs and outputs. Participants must extract a gate netlist from an unlabeled GDS layout file, determine the circuit's purpose, and find the input that drives the [success] signal high. Submissions close on September 4, 2026, with Jane Street asking participants not to feed puzzle files into AI tools or post spoilers before the deadline. A binary adder warm-up example using open-source PDKs and layout tools is provided to help participants understand GDS mapping. Jane Street plans to launch a subsequent competition later this year challenging participants to design their own chips, with select designs to be physically fabricated. The ASIC Reverse-Engineering Challenge The challenge provides participants with the final GDS mask containing the metal, routing, and active transistor layers of an ASIC along with sample inputs and outputs. To solve it, participants must reconstruct the gate-level netlist from the layout polygons, deduce the circuit's function, and simulate the system to discover the target string value that sets the [success] signal high after toggling [rst_n]. Jane Street notes the physical layout contains visual hints, one output-generating section can be bypassed for initial reverse engineering, and easter eggs are hidden throughout the repository. Guidelines, Resources, and Future Fabrication Contest Participants may collaborate and use AI to write auxiliary scripts or complete the warm-up, but direct AI analysis of the puzzle files and spoiler writeups before the September 4, 2026 deadline are disallowed. For newcomers, a warm-up package featuring a binary adder's Verilog source, netlist, and GDS is available to explore with open-source tools like KLayout and Magic VLSI. Jane Street also announced that later this year it will host a competition inviting participants to design original chips, with the most compelling entries being sent for physical fabrication.

Jane Street推出ASIC逆向工程谜题并预告芯片设计制造大赛 Jane Street发布了一项硬件逆向工程谜题，仅向参与者提供芯片的版图文件（GDS），要求从中还原网表并破解最终字符串。该挑战提交截止日期为2026年9月4日，官方还预告后续将启动定制芯片设计竞赛并将优秀作品实际流片制造。 谜题提供了一款未标注的ASIC芯片最终光刻掩模版图（GDS文件）及样本输入输出，要求逆向提取网表并推导最终目标字符串。 参与者需通过版图布局线索与电路仿真求解，当信号success变高时代表解答正确，提交截止时间为2026年9月4日。 规则允许使用AI编写辅助脚本，但禁止直接向AI投喂谜题文件或用其生成报告，且提交截止前不得公开剧透。 官方提供了二进制加法器范例作为入门热身，并预告年内将举办芯片设计大赛，届时最有趣的参赛方案将真正流片制造。 谜题核心与逆向流程 现代芯片从Verilog等硬件描述语言经逻辑综合生成门级网表，再经EDA工具布局布线后形成包含所有多边形几何信息的GDS文件并交由晶圆厂代工。Jane Street此次仅提供一款ASIC的最终掩模版图和测试输入输出。解题者需从布局中恢复网表、推断电路功能，再通过电路仿真找到使success信号变高所需的特定输入，进而得出最终字符串。 参与规则与入门指引 谜题基于开源PDK设计，参与者可使用KLayout或Magic VLSI等开源工具查看版图。官方在代码仓库中附带了一个包含Verilog源码、网表和GDS文件的二进制加法器，供解题者熟悉映射关系和测试自建工具。Jane Street允许使用AI协助编写解题脚本或代码，但禁止直接投喂谜题数据或代写报告，同时要求在2026年9月4日提交截止前不要公开答案或完整报告。 后续真实流片竞赛预告 Jane Street表示本次逆向谜题是后续行动的热身。今年晚些时候，其硬件团队将启动一项自研芯片设计竞赛，表现最突出的设计作品将获得实际流片制造的机会，参赛者可在现实中对实体芯片进行测试。

Earlier this year we published a puzzle that handed you a complete neural network and asked you to figure out what it did. The response was great, so we’ve made another one! This time, we’re going much deeper down the tech stack. For this puzzle we’ve designed a chip, but we’re only giving you the layout. A crash course in how chips get made Modern chips start life as code. A hardware designer describes a circuit in a hardware description language like Verilog, which gets synthesized into a netlist of logic gates—NANDs, NORs, XORs, flip-flops. Then electronic design automation tools place and route those gates: they pick a physical location for every gate on the die and draw the metal wires that connect them, across many stacked routing layers connected by vias. The end result is a GDS file: a geometric description of every polygon on every layer of the chip, from the transistors that do the actual logic to all the metal on top of them. That’s the file a foundry such as Intel or TSMC uses to fabricate the physical silicon. The GDS is, in a very real sense, the chip. Everything the circuit does is in there. The tricky part: nothing is labeled! The puzzle We’ve designed an ASIC, and we’re giving you its final mask: all of its metal, routing, and active transistor layers, along with some sample inputs and outputs. Your job is to reverse engineer it. First, recover a netlist from the layout. Then figure out the circuit’s true purpose. And then comes the puzzle within the puzzle: once you understand what the chip does, use it to tease out the output it’s looking for, and find the string value that’s your final answer. You can find everything you need here . Some pointers for getting started: The circuit is physically arranged to hint at its functionality, so look closely at the layout! There is one section of the design that is used to generate the output but does not affect the [success] output. You can safely ignore it for the initial reverse-engineering steps. You’ll need to come up with a way to simulate the underlying circuit to test your solution and get the final output! You’ll know you have the correct solution when the [success] output signal goes high. Don’t forget to toggle [rst_n] before each input attempt. We hid a few fun Easter eggs in the circuit and in the repository (including in parts you don’t need to look at to solve the main puzzle), see if you can spot them once you’re done with the puzzle. Once you figure it out, submit your answer here along with a brief description of how you did it. Submissions close on September 4th, 2026. Feel free to collaborate with friends on the puzzle, but please refrain from posting spoilers (or a full writeup) online until the submissions are closed. If you do publish your solution (on a personal blog or repository) after submissions are closed, email us and we may include the link in our follow-up post! Please don’t feed the puzzle files directly into an AI tool, nor use it to generate your writeups. Feel free to use AI for writing any scripts or code you may need as part of solving the puzzle, though! It’s also fair game to use AI to work through the warm-up puzzle, see below. If you have questions as you go, please reach out to asic-puzzle@janestreet.com — we can’t give hints, but we’re happy to help otherwise. We’ll feature the most interesting writeups and techniques in a follow-up post, and send swag for our favorite solutions. A warm-up If you’ve never opened a GDS file before, don’t worry: most people haven’t either. To help you get started, we’re providing a small worked example: a simple binary adder, with its Verilog source, its gate-level netlist, and the resulting GDS. You can use it to get familiar with how a circuit maps onto a layout, and to test any tools you build before pointing them at the real puzzle. The warm-up files are available in the puzzle repository . Everything you need is free and open source: the design uses an open-source PDK, and tools like KLayout or Magic VLSI will happily open the GDS and let you poke around the layers. And a bigger challenge is coming Consider this puzzle a warm-up of its own. Later this year we’ll be launching a competition where, instead of reverse engineering our chip, we’ll challenge you to design your own - and the most interesting entries will actually get fabricated, so you can test your chip in real life. Stay tuned—we’ll announce the details here on the blog in the coming months. Hardware at Jane Street The hardware team at Jane Street designs FPGAs and ASICs that run some of the fastest trading systems in the world, and the day-to-day work is full of puzzles just like this one: staring at a sea of gates, timing reports, or waveforms and slowly teasing out what’s really going on. These problems are hard in a way that’s deeply satisfying to solve, and honestly, it’s a big part of why we like working here. If that sounds intriguing, some ways of learning more: Check out our hardware (FPGA and ASIC) internships and full-time roles. Read about Hardcaml (our open-source OCaml hardware design libraries) On the academic side, read about our visiting researcher and graduate fellowship programs. If you just want to stay in touch, you can fill out this form .