NVIDIA Introduces Vera CPU to Address Agentic AI Fleet Workload Dynamics

NVIDIA Introduces Vera CPU to Address Agentic AI Fleet Workload Dynamics Production telemetry reveals that agentic AI workloads are characterized by long sequential reasoning chains interrupted by intermittent parallel bursts. NVIDIA positioned its Vera CPU as a balanced single-design solution to handle both latency-sensitive critical paths and high-concurrency fan-outs without stranding memory or compute resources. Telemetry across 163,594 agentic sessions showed that over 97% had unique trajectory profiles, preventing efficient fleet right-sizing with multiple specialized CPU models. Agentic tasks depend predominantly on a sequential latency-bound critical path punctuated by brief tool and sub-agent fan-out bursts. Temporarily turning off cores to boost single-threaded speed can strand up to 1.5 TB of memory capacity (8 GB per core), carrying a steep TCO penalty. Equipped with Olympus cores, NVIDIA's Vera CPU is estimated to achieve up to 1.5x the per-core agentic performance of AMD Venice across SPEC CPU 2026 compiler, static analysis, and Python tests. Telemetry and the Shape of Agentic Trajectories Agentic AI sessions are defined by length (reasoning steps, retries, and tool calls) and width (concurrent operations such as retrieval or sub-agents). Despite wide fan-outs, analysis of real-world runs, including a 33-minute Claude Code trace, indicates that sessions spend the vast majority of wall-clock time waiting on sequential dependency chains. Because the main agent must wait for parallel operations to complete before continuing, minimizing end-to-end latency depends on strong per-thread performance alongside sufficient thread concurrency. Resource Allocation and Hardware Trade-offs Targeting high raw core counts often forces CPUs to sacrifice the single-thread throughput required by the agent's critical path. Conversely, disabling compute cores to elevate single-thread clocks can strand attached DRAM—up to 8 GB per core and 1.5 TB total—imposing a significant total cost of ownership penalty. Efficient fleet economics therefore require a balance that optimizes completed user sessions rather than isolated single-thread or maximum-core metrics. NVIDIA Vera CPU Architecture and Performance The NVIDIA Vera CPU utilizes Olympus cores designed with a wide front end, deep out-of-order execution, advanced branch prediction, and a high-bandwidth memory subsystem. This monolithic architecture sustains per-thread responsiveness under full socket utilization while absorbing transient bursts of sub-agents and tool calls. Internal July 2026 estimates based on SPEC CPU 2026 benchmarks project Vera delivering up to 1.5x the per-core performance of AMD Venice across typical agentic workloads.

NVIDIA推出Vera CPU以应对智能体AI集群的计算挑战 NVIDIA针对智能体AI（Agentic AI）长依赖链与突发并发混合的工作负载特征，推出了采用Olympus核心的Vera CPU，通过兼顾高单线程性能与高并发吞吐量来优化集群总体拥有成本。 163,594个智能体生产会话遥测显示，超97%的会话轨迹特征互不相同，工作负载具有高度不可预测性。 智能体执行以严格受制于延迟的漫长串行推理链为主，伴随偶发的子任务并发扇出，单纯堆叠核心或关闭核心会损害总体完成时间或造成高达1.5 TB的内存资源闲置。 基于Olympus核心的Vera CPU针对典型智能体工作负载，在SPEC CPU 2026估算基准测试中单核性能达到AMD Venice竞品的最高1.5倍。 智能体工作负载的瓶颈与特征 基于超16万个会话的生产数据，智能体AI呈现出独特的执行轨迹：主体任务需要经历漫长的串行步骤、工具调用和子任务重试，整体会话时长主要受制于顺序链条的单线程延迟；同时，工作流中又夹杂着短暂的并发工具调用与沙盒运行。如果为了核心密度而牺牲单线程性能，或者通过关闭核心换取提频（可能导致每核8 GB、整机最高1.5 TB的内存闲置），均无法平衡全流程的执行效率。 Vera CPU架构对复杂轨迹的适配 NVIDIA Vera CPU搭载Olympus核心，具备宽前端、先进分支预测、深乱序执行和高带宽内存子系统，在整颗CPU处于满载状态下依然能维持强劲的单线程执行速度。内部测试估算显示，在涵盖编译器、静态分析及Python等典型智能体负载的SPEC CPU 2026评估中，其单核性能最高达AMD Venice竞品的1.5倍。该单一设计点有助于避免资源闲置，提升AI数据中心的整体任务完成效率。

AI factories are interconnected systems where fleet economics depend on how efficiently the entire stack converts power and capital into completed agent tasks. While GPUs run the models, CPUs handle orchestration, tool execution, and sandboxed computation. Unlike conventional computing with stable runtime profiles, agentic workloads are unpredictable and highly variable. Based on telemetry from 163,594 agentic sessions, over 97% of sessions showed unique trajectory profiles (Figure 1). This variability makes it impractical to right-size a fleet using multiple specialized CPU design points. Figure 1. Telemetry data from 163,594 agentic sessions showing over 97% unique profile s Production telemetry also reveals how these diverse trajectories unfold: across sessions, execution follows a long sequential chain of reasoning interspersed with sporadic bursts of parallel work. This real-world data shows that the dominant sequential path is strictly latency-bound—governing overall session completion time—while transient fan-out demands a combination of available thread concurrency and low-latency per-thread execution. Rather than fragmenting a fleet by planning around isolated tool-calling scenarios, AI factories need a single, balanced CPU design point. The NVIDIA Vera CPU is architected for this balance—delivering top per-core performance on typical agentic workloads to accelerate the critical path while absorbing intermittent fan-out bursts. The following sections examine the telemetry behind these agent trajectories and show how the Vera CPU’s balanced architecture optimizes real-world fleet economics. Optimizing along the critical path of agentic trajectories The shape of an agentic trajectory is defined by its length and width (Figure 2). Length: How many reasoning steps, tool calls, retries, and sub-tasks are required before the agent resolves a turn. Width : How much work fans out at each stage—concurrent tool calls, retrieval operations, sandboxes, or sub-agents. Figure 2. Agent trajectories vary in both execution depth and parallel width A session can have substantial width and still spend most of its wall-clock time waiting on the sequential chain, because parallel bursts are transient while the underlying dependency chain persists throughout the run. Even during wide fan-outs, per-thread latency remains critical. The main agent frequently idles until those parallel tasks complete before advancing to the next step. A CPU fleet must optimize for the full trajectory: providing enough concurrency to absorb fan-out bursts alongside the strong per-thread performance needed to accelerate the sequential path that ultimately determines end-to-end completion time. This is why the relevant optimization target for an agentic CPU fleet is the total number of completed user sessions, not raw core count. High-core-count systems might appear efficient on paper, but they often force a trade-off. To hit core density targets, they sacrifice the single-thread performance required to minimize latency on the agent’s critical path. Agentic workflows suffer when forced to run these sequential, latency-sensitive tasks on lower-performance cores, or when they encounter high synchronization overhead across massively parallel, heterogeneous clusters. A balanced CPU for agent workloads must pair enough cores to absorb concurrent tool execution and sub-agent fan-out with strong single-thread performance that accelerates the sequential steps that dominate total agent latency. What real agent sessions look like This can be tested against real agent telemetry. In the real-world Claude Code session shown in Figure 3, the main agent advances through a long sequential trajectory for most of the 33-minute run. Figure 3. Agentic workloads combine long sequential execution with brief sub-agent fan-out bursts The telemetry shows both sides of the agentic workload shape: meaningful fan-out and a long dependency chain. Sub-agent activity creates bursts of parallel work that must be served quickly, but the full user turn still advances through an ordered main trajectory in which each step unlocks the next. The CPU fleet therefore needs enough concurrency to absorb fan-out bursts without delay, while also sustaining strong per-thread performance on the latency-sensitive path that determines end-to-end completion time. Figure 4. Turning off cores to increase single-threaded performance can strand up to 1.5 TB of memory capacity At any given moment, a CPU can effectively “turn off” cores to temporarily boost single-threaded performance. This can leave 8 GB per core unused and impose a significant memory TCO penalty (Figure 4). A well-balanced CPU design optimizes for the entire workload trajectory rather than any single phase in isolation. By combining strong per-thread responsiveness with meaningful concurrency, ample memory bandwidth, and efficient power use, this approach maximizes completed user turns while using CPU cores, DRAM, GPU HBM, and the broader memory hierarchy efficiently. How Vera CPUs deliver this balance The Vera CPU is built for this operating point, with NVIDIA Olympus cores designed to sustain strong per-thread performance while the full CPU is active. The wide front end, advanced branch prediction, deep out-of-order execution, and high-bandwidth memory subsystem help each core maintain forward progress across large code footprints, branch-heavy control flow, dynamic runtimes, and dependency-heavy execution. The Claude Code data above shows that agentic workloads need this same balance: concurrency to absorb fan-out, and per-thread speed to keep the dominant sequential path moving. The estimated SPEC CPU® 2026 results in Figure 5 put that design point to the test. Highlighting Vera CPU’s loaded per-core performance across typical agentic workloads, including compiler, static analysis, and Python benchmarks—and showing how Olympus handles concurrency without sacrificing the performance needed on the agent critical path—NVIDIA Vera CPU delivers up to 1.5x the agentic performance of the latest competition. Figure 5. NVIDIA Vera CPU is estimated to deliver 1.5x the per-core performance of AMD Venice across four agentic workloads An optimal agentic fleet just needs a single CPU design point Vera provides a more efficient CPU foundation for agentic AI fleets because it is built for the full range of real agent trajectories. Strong single-thread performance at full socket load keeps the latency-sensitive sequential path moving, while high concurrency across cores and ample memory bandwidth absorb intermittent tool-call and sub-agent fan-out. Vera CPU’s low-latency monolithic architecture further reduces topology-driven stalls and variability across these phases. This balanced design helps avoid stranded resources: cores remain productive during both sequential work and parallel bursts, and the memory attached to those cores is used effectively rather than remaining tied to underutilized compute. It also reduces the need to divide the fleet among multiple specialized CPU design points to accommodate unpredictable tool-calling patterns. The result is a CPU platform that converts compute, memory bandwidth, and power into more completed agent turns—improving AI factory output and fleet economics at scale. To learn more about the NVIDIA Vera CPU architecture and performance, refer to the NVIDIA Vera CPU Whitepaper . NVIDIA Vera SPEC CPU® 2026 results measured internally in July 2026. Refer to this NVIDIA Vera CPU Whitepaper for details on performance measurements and configuration. AMD Venice results are based on link . Individual workload performance for Venice was estimated based on SPECrate®2026_int_base score 2070 with components normalized based on internal Turin measurements. Results may vary. SPEC®, SPEC CPU®, and SPECrate® are registered trademarks of the Standard Performance Evaluation Corporation ( www.spec.org ). Acknowledgements This work was made possible by the expertise and insights of Ivan Goldwasser, Diana Aung, Hannah Coutand, Ian Finder, Benjamin Klieger, Arnav Jaiswal, Dylan Mitic, and many others.